A1280A-PQ160I

更新时间： 2024-02-27 07:39:36

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A1280A-PQ160I 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
包装说明：	PLASTIC, QFP-160	Reach Compliance Code：	compliant
风险等级：	5.83	JESD-30 代码：	S-PQFP-G160
JESD-609代码：	e0	长度：	28 mm
湿度敏感等级：	3	可配置逻辑块数量：	1232
等效关口数量：	8000	端子数量：	160
最高工作温度：	125 °C	最低工作温度：	-55 °C
组织：	1232 CLBS, 8000 GATES	封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装形状：	SQUARE
封装形式：	FLATPACK	峰值回流温度（摄氏度）：	225
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY	认证状态：	Not Qualified
座面最大高度：	4.1 mm	最大供电电压：	5.5 V
最小供电电压：	4.5 V	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	MILITARY	端子面层：	TIN LEAD
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	28 mm	Base Number Matches：	1

1 – ACT 2 Family Overview

General Description

The ACT 2 family represents Actel’s second generation of field programmable gate arrays

(FPGAs). The ACT 2 family presents a two-module architecture, consisting of C-modules and S-

modules. These modules are optimized for both combinatorial and sequential designs. Based on Actel’s

patented channeled array architecture, the ACT 2 family provides significant enhancements to gate

density and performance while maintaining downward compatibility with the ACT 1 design environment

and upward compatibility with the ACT 3 design environment. The devices are implemented in silicon

gate, 1.0-μm, two-level metal CMOS, and employ Actel’s PLICE® antifuse technology. This revolutionary

architecture offers gate array design flexibility, high performance, and fast time-to-production with user

programming. The ACT 2 family is supported by the Designer and Designer Advantage Systems, which

offers automatic pin assignment, validation of electrical and design rules, automatic placement and

routing, timing analysis, user programming, and diagnostic probe capabilities. The systems are

supported on the following platforms: 386/486™ PC, Sun™, and HP™ workstations. The systems

provide CAE interfaces to the following design environments: Cadence, Viewlogic^®, Mentor Graphics ,

and OrCAD™.

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