Datasheet > A1225XL-1PQ100I

A1225XL-1PQ100I

更新时间： 2022-12-01 20:25:35

品牌	Logo	应用领域
美高森美 - MICROSEMI		栅
页数	文件大小	规格书
84页	4582K
描述
Field Programmable Gate Array, 170MHz, 451-Cell, CMOS, PQFP100,

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A1225XL-1PQ100I 数据手册

Integrator Series FPGAs: 1200XL and 3200DX Families

3200DX devices contain a third type of logic module,

D-modules, which are arranged around the periphery of the

device. D-modules contain wide-decode circuitry which

provides a fast, wide-input AND function similar to that

found in product term architectures (Figure 3). The

D-module allows 3200DX devices to perform wide-decode

functions at speeds comparable CPLDs and PAL devices.

The output of the D-module has a programmable inverter

for active HIGH or LOW assertion. The D-module output is

hard-wired to an output pin or can be fed back into the

array to be incorporated into other logic.

modules can be cascaded together to form memory spaces

of user-definable width and depth. A block diagram of the

3200DX dual-port SRAM block is shown in Figure 4.

7 Inputs

Hard-Wire to I/O

Programmable

Inverter

Dual-Port SRAM Modules

Several 3200DX devices contain dual-port SRAM modules

that have been optimized for synchronous or asynchronous

applications. The SRAM modules are arranged in 256-bit

blocks which can be configured as 32x8 or 64x4 (refer to

“Integrator Series Product Profile Family” on page 1 for the

number of SRAM blocks within a particular device). SRAM

Feedback to Array

Figure 3 • D-Module Implementation

WD[7:0]

Latches

[7:0]

[5:0]

RDAD[5:0]

SRAM Module

32 x 8 or 64 x 4

Latches

Read

Port

Logic

Write

Port

Logic

(256 Bits)

WRAD[5:0]

[5:0]

Read

Logic

Latches

REN

RCLK

MODE

BLKEN

WEN

RD[7:0]

Write

Logic

Routing Tracks

WCLK

Figure 4 • 3200DX Dual-Port SRAM Block

The 3200DX SRAM modules are true dual-port structures

containing independent READ and WRITE ports. Each

SRAM module contains six bits of read and write addressing

(RDAD[5:0] and WRAD[5:0], respectively) for 64x4 bit

blocks. When configured in byte mode, the highest order

address bits (RDAD5 and WRAD5) are not used. The read

and write ports of the SRAM block contain independent

clocks (RCLK and WCLK) with programmable polarities

offering active HIGH or LOW implementation. The SRAM

block contains eight data inputs (WD[7:0]) and eight

outputs (RD[7:0]) which are connected to segmented

vertical routing tracks.

The 3200DX dual-port SRAM blocks provide an optimal

solution for high-speed buffered applications requiring fast

FIFO and LIFO queues. Actel’s ACTgen Macro Builder

provides the capability to quickly design memory functions,

Discontinued – v3.0

1...4 5 678 9 10...84

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