Datasheet > A1010B-VQG80C

A1010B-VQG80C

更新时间： 2024-01-23 21:35:56

品牌	Logo	应用领域
ACTEL		时钟栅可编程逻辑
页数	文件大小	规格书
24页	163K
描述
Field Programmable Gate Array, 295 CLBs, 1200 Gates, 45MHz, 295-Cell, CMOS, PQFP80, MO-136, VQFP-80

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A1010B-VQG80C 技术参数

是否Rohs认证：	符合	生命周期：	Transferred
包装说明：	MO-136, VQFP-80	Reach Compliance Code：	compliant
风险等级：	5.78	其他特性：	MAX 57 I/OS
最大时钟频率：	45 MHz	CLB-Max的组合延迟：	4.5 ns
JESD-30 代码：	S-PQFP-G80	JESD-609代码：	e3
长度：	14 mm	湿度敏感等级：	3
可配置逻辑块数量：	295	等效关口数量：	1200
输入次数：	57	逻辑单元数量：	295
输出次数：	57	端子数量：	80
最高工作温度：	70 °C	最低工作温度：
组织：	295 CLBS, 1200 GATES	封装主体材料：	PLASTIC/EPOXY
封装代码：	TQFP	封装等效代码：	TQFP80,.6SQ
封装形状：	SQUARE	封装形式：	FLATPACK, THIN PROFILE
峰值回流温度（摄氏度）：	260	电源：	5 V
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY	认证状态：	Not Qualified
座面最大高度：	1.2 mm	子类别：	Field Programmable Gate Arrays
最大供电电压：	5.25 V	最小供电电压：	4.75 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	MATTE TIN	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	40	宽度：	14 mm
Base Number Matches：	1

A1010B-VQG80C 数据手册

™

A C T

1 S e r i e s F P G A s

A C T 1 A r r a y P e r f o r m a n c e

source 10 mA at TTL levels. See Electrical Specifications for

additional I/O buffer specifications.

T e m p e r a t u r e a n d Vo lt a g e E ffe c t s

Worst-case delays for ACT 1 arrays are calculated in the same

manner as for masked array products. A typical delay

parameter is multiplied by a derating factor to account for

temperature, voltage, and processing effects. However, in an

ACT 1 array, temperature and voltage effects are less

dramatic than with masked devices. The electrical

characteristics of module interconnections on ACT 1 devices

remain constant over voltage and temperature fluctuations.

D e v i c e O r g a n i z a t i o n

ACT 1 devices consist of a matrix of logic modules arranged in

rows separated by wiring channels. This array is surrounded

by a ring of peripheral circuits including I/O buffers,

testability circuits, and diagnostic probe circuits providing

real-time diagnostic capability. Between rows of logic

modules are routing channels containing sets of segmented

metal tracks with PLICE antifuses. Each channel has 22

signal tracks. Vertical routing is permitted via 13 vertical

tracks per logic module column. The resulting network allows

arbitrary and flexible interconnections between logic

modules and I/O modules.

As a result, the total derating factor from typical to

worst-case for a standard speed ACT 1 array is only 1.19 to 1,

compared to 2 to 1 for a masked gate array.

Lo g ic Mo d u le S iz e

Logic module size also affects performance. A mask

programmed gate array cell with four transistors usually

implements only one logic level. In the more complex logic

module (similar to the complexity of a gate array macro) of

an ACT 1 array, implementation of multiple logic levels

within a single module is possible. This eliminates interlevel

wiring and associated RC delays. The effect is termed “net

compression.”

P r o b e P i n

ACT 1 devices have two independent diagnostic probe pins.

These pins allow the user to observe any two internal signals

by entering the appropriate net name in the diagnostic

software. Signals may be viewed on a logic analyzer using

Actel’s Actionprobe^®diagnostic tools. The probe pins can

also be used as user-defined I/Os when debugging is finished.

O r d e r i n g I n f o r m a t i o n

A1010

–

Application (Temperature Range)

C = Commercial (0 to +70°C)

= Industrial (–40 to +85°C)

M = Military (–55 to +125°C)

B = MIL-STD-883

Package Lead Count

Package Type

PL = Plastic J-Leaded Chip Carriers

PQ = Plastic Quad Flatpacks

CQ = Ceramic Quad Flatpack

PG = Ceramic Pin Grid Array

VQ = Very Thin Quad Flatpack

Speed Grade

Blank = Standard Speed

–1

–2

–3

= Approximately 15% faster than Standard

= Approximately 25% faster than Standard

= Approximately 35% faster than Standard

Die Revision

B = 1.0 micron CMOS Process

Part Number

A1010 = 1200 Gates (5 V)

A1020 = 2000 Gates (5 V)

A10V10 = 1200 Gates (3.3 V)

A10V20 = 2000 Gates (3.3 V)

1 -2 8 5

1 234 5 6 7...24

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