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A1010B-PQ100C

更新时间： 2024-02-25 21:15:42

品牌	Logo	应用领域
ACTEL		现场可编程门阵列可编程逻辑栅时钟
页数	文件大小	规格书
98页	2009K
描述
HiRel FPGAs

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技术参数
数据手册

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A1010B-PQ100C 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	PLASTIC, MO-108, QFP-100	Reach Compliance Code：	compliant
风险等级：	5.87	其他特性：	MAX 57 I/OS
最大时钟频率：	40.5 MHz	CLB-Max的组合延迟：	4.5 ns
JESD-30 代码：	R-PQFP-G100	JESD-609代码：	e0
长度：	20 mm	湿度敏感等级：	3
可配置逻辑块数量：	295	等效关口数量：	1200
输入次数：	57	逻辑单元数量：	295
输出次数：	57	端子数量：	100
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	295 CLBS, 1200 GATES	封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装等效代码：	QFP100,.7X.9
封装形状：	RECTANGULAR	封装形式：	FLATPACK
峰值回流温度（摄氏度）：	225	电源：	5 V
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY	认证状态：	Not Qualified
座面最大高度：	3.4 mm	子类别：	Field Programmable Gate Arrays
最大供电电压：	5.5 V	最小供电电压：	4.5 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	14 mm
Base Number Matches：	1

A1010B-PQ100C 数据手册

Product Family Profile

Family

Device

ACT 2

ACT 1

A1240A

A1280A

A1010B

A1020B

Capacity

System Gates

Logic Gates

SRAM Bits

6,000

4,000

12,000

8,000

1,800

1,200

3,000

2,000

Logic Modules

S-Modules

C-Modules

Decode

684

348

336

1,232

624

608

295

—

295

547

—

547

Flip-Flops (maximum)

User I/Os (maximum)

568

104

998

140

147

273

Packages (by pin count)

CPGA

CQFP

132

—

176

172

—

Performance

20 MHz

System Speed (maximum)

40 MHz

High-Reliability, Low-Risk Solution

junction temperatures. Actel’s non-PLD architecture delivers

lower dynamic operating current. Our reliability tests show a

very low failure rate of 6.6 FITs at 90°C junction temperature

with no degradation in AC performance. Special stress testing

at wafer test eliminates infant mortalities prior to packaging.

Actel builds the most reliable field programmable gate arrays

(FPGAs) in the industry, with overall antifuse reliability

ratings of less than 10 Failures-In-Time (FITs),

corresponding to a useful life of more than 40 years. Actel

FPGAs have been production proven, with more than five

million devices shipped and more than one trillion antifuses

manufactured. Actel devices are fully tested prior to

shipment, with an outgoing defect level of less than 100 ppm.

(Further reliability data is available in the Actel Device

Reliability Report, at http://www.actel.com/hirel).

Minimized Security Risk

Reverse engineering of programmed Actel devices from

optical or electrical data is extremely difficult. Programmed

antifuses cannot be identified from a photograph or by using

an SEM. The antifuse map cannot be deciphered either

electrically or by microprobing. Each device has a silicon

signature that identifies its origins, down to the wafer lot and

fabrication facility.

Benefits

Minimized Cost Risk

Minimized Testing Risk

With Actel’s line of development tools, designers can produce

as many chips as they choose for just the cost of the device

itself. There will be no NRE charges to cut into the

development budget each time a new design is tried.

Unprogrammed Actel parts are extensively tested at the

factory. Routing tracks, logic modules, and programming,

debug and test circuits are 100 percent tested before

shipment. AC performance is ensured by special speed path

tests, and programming circuitry is verified on test antifuses.

During the programming process, an algorithm is run to

ensure that all antifuses are correctly programmed. In

addition, Actel’s Silicon Explorer diagnostic tool uses

ActionProbe circuitry, allowing 100 percent observability of

all internal nodes to check and debug the design.

Minimized Time Risk

After the design is entered, placement and routing is

automatic, and programming the device takes only about 5 to

15 minutes for an average design. Designers save time in the

design entry process by using tools with which they are

familiar.

Minimized Reliability Risk

Actel FPGA Description

The PLICE antifuse is a one-time programmable, nonvolatile

connection. Since Actel devices are permanently

programmed, no downloading from EPROM or SRAM storage

is required. Inadvertent erasure is impossible, and there is no

need to reload the program after power disruptions.

Fabrication using a low-power CMOS process means cooler

The Actel families of FPGAs offer a variety of packages,

speed/performance characteristics, and processing levels for

use in all high reliability and military applications. Devices

are implemented in a silicon gate, two-level metal CMOS

process, utilizing Actel’s PLICE antifuse technology. This

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与A1010B-PQ100C相关器件

型号	品牌	描述	获取价格	数据表
A1010B-PQ100I	MICROSEMI	Field Programmable Gate Array, 547 CLBs, 2000 Gates, 40.5MHz, 295-Cell, CMOS, PQFP100, PLA	获取价格
A1010B-PQ100I	ACTEL	Field Programmable Gate Array, 295 CLBs, 1200 Gates, 40.5MHz, 295-Cell, CMOS, PQFP100, PLA	获取价格
A1010B-PQG100C	ACTEL	Field Programmable Gate Array, 295 CLBs, 1200 Gates, 45MHz, 295-Cell, CMOS, PQFP100, PLAST	获取价格
A1010B-PQG100I	ACTEL	Field Programmable Gate Array, 295 CLBs, 1200 Gates, 40.5MHz, 295-Cell, CMOS, PQFP100, PLA	获取价格
A1010BSTDCQ84B	ETC	ASIC	获取价格
A1010BSTDCQ84C	ETC	ASIC	获取价格

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