Datasheet > 存储 > SRAM> 71V3558S200PFG

71V3558S200PFG

更新时间： 2024-02-19 03:19:22

品牌	Logo	应用领域
艾迪悌 - IDT		计数器存储内存集成电路静态存储器时钟
页数	文件大小	规格书
28页	643K
描述
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs

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技术参数
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71V3558S200PFG 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	TQFP
包装说明：	14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100	针数：	100
Reach Compliance Code：	unknown	ECCN代码：	3A991
HTS代码：	8542.32.00.41	风险等级：	5.19
Is Samacsys：	N	最长访问时间：	3.2 ns
最大时钟频率 (fCLK)：	200 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PQFP-G100	JESD-609代码：	e3
长度：	20 mm	内存密度：	4718592 bit
内存集成电路类型：	ZBT SRAM	内存宽度：	18
湿度敏感等级：	3	功能数量：	1
端子数量：	100	字数：	262144 words
字数代码：	256000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	256KX18	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装等效代码：	QFP100,.63X.87	封装形状：	RECTANGULAR
封装形式：	FLATPACK, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	260	电源：	3.3 V
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大待机电流：	0.04 A	最小待机电流：	3.14 V
子类别：	SRAMs	最大压摆率：	0.4 mA
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Matte Tin (Sn) - annealed	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	14 mm
Base Number Matches：	1

71V3558S200PFG 数据手册

IDT71V3556S/XS

IDT71V3558S/XS

IDT71V3556SA/XSA

128K x 36, 256K x 18

3.3V Synchronous ZBT SRAMs

3.3V I/O, Burst Counter

Pipelined Outputs

IDT71V3558SA/XSA

Description

Features

◆

TheIDT71V3556/58are3.3Vhigh-speed4,718,592-bit(4.5Mega-

bit) synchronous SRAMS. They are designed to eliminate dead bus

cycles when turning the bus around between reads and writes, or

writes and reads. Thus, they have been given the name ZBT^TM, or

Zero Bus Turnaround.

128K x 36, 256K x 18 memory configurations

◆

Supports high performance system speed - 200 MHz (x18)

(3.2 ns Clock-to-Data Access)

Supports high performance system speed - 166 MHz (x36)

◆

(3.5 ns Clock-to-Data Access)

ZBT^TMFeature - No dead cycles between write and read

◆

Address and control signals are applied to the SRAM during one

clock cycle, and two cycles later the associated data cycle occurs, be

it read or write.

cycles

◆

Internally synchronized output buffer enable eliminates the

The IDT71V3556/58 contain data I/O, address and control signal

registers. Output enable is the only asynchronous signal and can be

used to disable the outputs at any given time.

need to control OE

Single R/W (READ/WRITE) control pin

Positive clock-edge triggered address, data, and control

◆

A Clock Enable (CEN) pin allows operation of the IDT71V3556/58

to be suspended as long as necessary. All synchronous inputs are

ignored when (CEN) is high and the internal device registers will hold

their previous values.

There are three chip enable pins (CE¹, CE2, CE2) that allow the

user to deselect the device when desired. If any one of these three are

not asserted when ADV/LD is low, no new memory operation can be

initiated. However, any pending data transfers (reads or writes) will be

completed.Thedatabuswilltri-statetwocyclesafterchipisdeselected

orawriteisinitiated.

signal registers for fully pipelined applications

4-word burst capability (interleaved or linear)

Individual byte write (BW1 - BW4) control (May tie active)

Three chip enables for simple depth expansion

3.3V power supply (±5%), 3.3V I/O Supply (VDDQ)

Optional- Boundary Scan JTAG Interface (IEEE 1149.1

compliant)

Packaged in a JEDEC standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch

ball grid array (fBGA)

◆

Pin Description Summary

-A17

Address Inputs

Input

Output

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enables

, CE

Output Enable

R/W

Read/Write Signal

Clock Enable

CEN

Individual Byte Write Selects

Clock

, BW

CLK

ADV/LD

LBO

Advance burst address / Load new address

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

Synchronous

Static

TMS

TDI

Synchronous

N/A

TCK

Test Clock

TDO

Test Data Output

Synchronous

Asynchronous

Synchronous

Static

JTAG Reset (Optional)

Sleep Mode

TRST

I/O

-I/O31, I/OP1-I/OP4

Data Input / Output

Core Power, I/O Power

Ground

DD, VDDQ

Supply

Static

5281 tbl 01

OCTOBER 2010

DSC-5281/11

12 3 4 5 6 7...28

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