Datasheet > 252MIP

252MIP

更新时间： 2024-01-20 06:31:34

品牌	Logo	应用领域
艾迪悌 - IDT		光电二极管
页数	文件大小	规格书
9页	148K
描述
Clock Generator, CMOS, PDSO8

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技术参数
数据手册

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252MIP 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	包装说明：	SOP, SOP8,.25
Reach Compliance Code：	not_compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.92
JESD-30 代码：	R-PDSO-G8	JESD-609代码：	e0
湿度敏感等级：	1	端子数量：	8
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP8,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	峰值回流温度（摄氏度）：	240
电源：	3.3 V	认证状态：	Not Qualified
子类别：	Clock Generators	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn85Pb15)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	30
Base Number Matches：	1

252MIP 数据手册

ICS252

Field Programmable Dual Output SS VersaClock Synthesizer

Description

Features

The ICS252 is a low cost, dual-output, field

• 8-pin SOIC package

programmable clock synthesizer. The ICS252 can

generate two output frequencies from 314 kHz to 200

MHz using up to two independently configurable PLLs.

The outputs may employ Spread Spectrum techniques

to reduce system electro-magnetic interference (EMI).

• Two addressable registers

• Input crystal frequency of 5 to 27 MHz

• Clock input frequency of 3 to 150 MHz

• Output clock frequencies up to 200 MHz

• Configurable Spread Spectrum Modulation

™

Using ICS’ VersaClock software to configure the PLL

and output, the ICS252 contains a One-Time

Programmable (OTP) ROM to allow field

programmability. Programming features include 4

selectable configuration registers.

• Operating voltage of 3.3 V

• Replaces multiple crystals and oscillators

• Controllable output drive levels

• Advanced, low-power CMOS process

• Available in Pb (lead) free packaging

The device employs Phase-Locked Loop (PLL)

techniques to run from a standard fundamental mode,

inexpensive crystal, or clock. It can replace multiple

crystals and oscillators, saving board space and cost.

The device also has a power-down feature that

tri-states the clock outputs and turns off the PLLs when

the PDTS pin is taken low.

The ICS252 is also available in factory programmed

custom versions for high-volume applications.

Block Diagram

VDD

OTP

SEL

PLL1

PLL2

Divide

Logic

and

Output

Enable

Control

ROM

with

CLK1

CLK2

PLL

Values

Crystal

Oscillator

Crystal

GND

External capacitors

are required.

PDTS

MDS 252 B

Revision 011606

Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com

12 3 4 5 6 7...9

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