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252PMT PDF预览

252PMT

更新时间: 2024-11-06 20:10:47
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
11页 221K
描述
Clock Generator, 200MHz, CMOS, PDSO8, 0.150 INCH, SOIC-8

252PMT 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP,
针数:8Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.18JESD-30 代码:R-PDSO-G8
JESD-609代码:e0长度:4.9 mm
湿度敏感等级:1端子数量:8
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:200 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):240
主时钟/晶体标称频率:150 MHz认证状态:Not Qualified
座面最大高度:1.75 mm最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:20
宽度:3.9 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

252PMT 数据手册

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DATASHEET  
FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER  
ICS252  
Description  
Features  
The ICS252 is a low cost, dual-output, field programmable  
clock synthesizer. The ICS252 can generate two output  
frequencies from 314 kHz to 200 MHz using up to two  
independently configurable PLLs. The outputs may employ  
Spread Spectrum techniques to reduce system  
electro-magnetic interference (EMI).  
8-pin SOIC package  
Two addressable registers  
Input crystal frequency of 5 to 27 MHz  
Clock input frequency of 3 to 150 MHz  
Output clock frequencies up to 200 MHz  
Configurable Spread Spectrum Modulation  
Using ICS’ VersaClock software to configure the PLL and  
output, the ICS252 contains a One-Time Programmable  
(OTP) ROM to allow field programmability. Programming  
features include 4 selectable configuration registers.  
Operating voltage of 3.3 V  
Replaces multiple crystals and oscillators  
Controllable output drive levels  
The device employs Phase-Locked Loop (PLL) techniques  
to run from a standard fundamental mode, inexpensive  
crystal, or clock. It can replace multiple crystals and  
oscillators, saving board space and cost.  
Advanced, low-power CMOS process  
Available in RoHS 5 (green) or RoHS 6 (green and lead  
free) compliant package  
The device also has a power-down feature that tri-states the  
clock outputs and turns off the PLLs when the PDTS pin is  
taken low.  
The ICS252 is also available in factory programmed custom  
versions for high-volume applications.  
Block Diagram  
VDD  
OTP  
SEL  
PLL1  
PLL2  
Divide  
Logic  
and  
Output  
Enable  
Control  
ROM  
with  
CLK1  
CLK2  
PLL  
Values  
X1  
Crystal  
Oscillator  
Crystal  
X2  
GND  
External capacitors  
are required.  
PDTS  
IDT™ / ICS™ FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER 1  
ICS252  
REV C 061306  

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