FX802
DVSR CODEC
SERIAL
CLOCK
COMMAND
DATA
REPLY
DATA
XTAL/
CLOCK
AUDIO
IN
AUDIO
OUT
IRQ
XTAL
CS
AUDIO
BYPASS
CLOCK
C-BUS INTERFACE AND CONTROL LOGIC
GENERATOR
DECODER
OUTPUT
BIAS
V
STATUS
CONTROL
REGISTER
REGISTER
STORE
PLAY
COMMAND
BUFFER
COMMAND
BUFFER
ENCODE
CLOCK
DECODE
CLOCK
DATA
READ
DATA
WRITE
SPEECH
STORE
SPEECH
PLAY
POWER
ASSESS
MOD
DEMOD
COUNTER
COUNTER
COUNTERS
COUNTERS
ENCODER
CLOCK
DECODER
CLOCK
IDLE
PATTERN
DRAM CONTROL AND TIMING
DIRECT ACCESS CLOCKS and DATA
CAS
RAS 2 RAS 3 RAS 4
RAS 1
WE
VSS
VDD
VBIAS
A9
A8
A7
A6
A5
A4
A3/ECK
A2/DCK
A0/ENO
(ENCODER
OUT)
A1/ DEI
(DECODER
IN)
DRAM ADDRESS LINES
Fig.1 FX802 DVSR Codec
Brief Description
The FX802 DVSR Codec contains:
The FX802 may also be used without DRAM (as a “stand-
alone” CVSD Codec), in which case direct access is
provided to the CVSD Codec digital data and clock signals.
A Continuously Variable Slope Delta Modulation (CVSD)
encoder and decoder.
All functions are controlled by “C-BUS” commands from
the system µController.
Control and timing circuitry for up to 4Mbits of external
Dynamic Random Access Memory (DRAM).
The Storage, Recovery and Replay functions of the
FX802 can be used for:
“C-BUS” µProcessor interface and control logic.
When used with external DRAM, the FX802 has four primary
functions:
● Answering Machine applications, where an incoming
speech message is stored for later recall.
●
Speech Storage
● Busy Buffering, an outgoing speech message is stored
Speech signals present at the Audio Input may be digitized
by the CVSD encoder, and the resulting bit stream stored
in DRAM. This process also provides readings of input
power level for use by the system µController.
temporarily until the transmit channel becomes free.
● Automatic transmission of pre-recorded ‘Alarm’ or
status announcements.
● Time Domain Scrambling of speech messages.
● VOX control of transmitter functions.
●
Speech Playback
Previously digitized speech data may be read from DRAM
and converted back into analogue form by the CVSD
decoder.
● Temporary Data Storage applications, such as
buffering of over-air data transmissions.
On-chip the Delta Codec is supported by input and output
analogue switched-capacitor filters and audio output
switching circuitry. The DRAM control and timing circuitry
provides all the necessary address, control and refresh
signals to interface to external DRAM.
●
Data Storage
Digital data sent over the “C-BUS” from the system
µController may be stored in DRAM.
●
Data Retrieval
Digital data may be read from DRAM and sent over
“C-BUS” to the system µController.
The FX802 DVSR Codec is a low-power 5-volt CMOS LSI
device.
Speech storage and playback may be performed
concurrently with data storage or retrieval.
Publication D/802/4 December 1995