Features
Industry Standard Architecture
•
Emulates Many 20-Pin PALs
Low Cost Easy-to-Use Software Tools
High Speed Electrically Erasable Programmable Logic Devices
•
12 ns Maximum Pin-to-Pin Delay
Low Power - 25 µA Standby Power
CMOS and TTL Compatible Inputs and Outputs
•
•
Input and I/O Pin Keeper Circuits
Advanced Flash Technology
•
High
Reprogrammable
100% Tested
Performance
E2 PLD
High Reliability CMOS Process
•
20 Year Data Retention
100 Erase/Write Cycles
2,000V ESD Protection
200 mA Latchup Immunity
Commercial and Industrial Temperature Ranges
Dual Inline and Surface Mount Packages in Standard Pinouts
•
•
ATF16V8CZ
Block Diagram
Pin Configurations
Pin Name
Function
TSSOP Top View
CLK
I
Clock
ATF16V8CZ
Logic Inputs
Bidirectional Buffers
Output Enable
+5V Supply
I/CLK
I1
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
I/O
OE
VCC
I/O
I2
I/O
I3
I/O
I4
I/O
I5
I/O
I6
I/O
I7
I/O
I8
I/O
GND
I9/OE
DIP/SOIC
PLCC
Vcc
I/CLK
1
20
19
18
17
16
15
14
13
12
Vcc
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/CLK
I1
I/O
I2 I1
2
3
4
5
6
7
8
9
1
I2
I3
I4
I5
I6
I7
I8
I3
I4
I5
I6
I7
I/O
I/O
6
16 I/O
I/O
I/O
11
I8
I/O I/O
10
11
GND
I9/OE
GND I9/OE
Top view
Rev. 0453C/V16FZ-C–04/98