Datasheet > 9FG107YGLNT

9FG107YGLNT

更新时间： 2024-01-05 01:13:46

品牌	Logo	应用领域
艾迪悌 - IDT		外围集成电路
页数	文件大小	规格书
19页	335K
描述
Processor Specific Clock Generator

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技术参数
数据手册

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9FG107YGLNT 技术参数

生命周期：	Active	Reach Compliance Code：	compliant
风险等级：	5.77	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches：	1

9FG107YGLNT 数据手册

ICS9FG107

Programmable FTG for Differential P4^TMCPU, PCI-Express & SATA Clocks

I²C Table: Device Control Register, READ/WRITE ADDRESS (DC/DD)

Byte 0

Pin #

Name

Control Function

Type

PWD

Pin 27

Pin 5

Pin 44

Pin 7

FS3¹

Bit 7

Bit 6

Bit 5

Bit 4

FS2¹

FS1¹

See Frequency

Selection Table, Page 1

FS0¹

Spread Enable¹

Off

Hardware

Select

Driven

Down

Software

Select

Hi-Z

Pin 26

Bit 3

Enable Software Control of Frequency,

Spread Enable and Spread Type

DIF_STOP# drive mode

Bit 2

Bit 1

Bit 0

Notes:

DWNSPRD#¹

Center

Pin 45

1. These bits reflect the latched state of the corresponding pins at power up, but may be written to

if Byte 0, bit 2 is set to '1'. FS3 is the SEL14M_25M# pin.

I²C Table: Output Enable Register

Byte 1

Pin #

Name

PCICLK0

DIF_6

DIF_5

DIF_4

DIF_3

DIF_2

DIF_1

DIF_0

Control Function

Output Enable

Type

PWD

Stop Low

Disable

Enable

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

12,13

17,18

20,21

30,29

33,32

39,38

42,41

I²C Table: Output Stop Mode Register

Byte 2

Pin #

Name

PCICLK1

DIF_6

DIF_5

DIF_4

DIF_3

DIF_2

DIF_1

DIF_0

Control Function

Output Enable

Stop Mode

Type

PWD

Stop Low

Free-run

Enable

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

12,13

17,18

20,21

30,29

33,32

39,38

42,41

Stop-able

Stop Mode

IDT^TM/ICS^TMProgrammable FTG for Differential P4^TMCPU, PCI-Express & SATA Clocks

ICS9FG107

REV F 08/21/07

1...3 4 567 8 9...19

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