Datasheet > 9DB306LLFT

9DB306LLFT

更新时间： 2024-02-19 07:56:00

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
15页	309K
描述
Clock Driver

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9DB306LLFT 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
包装说明：	,	Reach Compliance Code：	compliant
风险等级：	5.84	Base Number Matches：	1

9DB306LLFT 数据手册

ICS9DB306

Integrated

Circuit

Systems, Inc.

PCI EXPRESS

JITTER

ATTENUATOR

TABLE 1. PIN DESCRIPTIONS

Number

Name

Type

Description

1, 14, 20

V_EE

Power

Negative supply pins.

PCIEXT1,

PCIEXC1

PCIEXT2,

PCIEXC2

2, 3

Output

Differential output pairs. LVPECL interface levels.

4, 5

Output

Power

Differential output pairs. LVPECL interface levels.

Core supply pins.

6, 9, 15, 28

V_CC

Output enable. When HIGH, forces true outputs (PCIEXTx) to go

7, 8

nOE0, nOE1

Input

Pulldown LOW and the inverted outputs (PCIEXCx) to go HIGH. When LOW,

outputs are enabled. LVCMOS/LVTTL interface levels.

PCIEXC3,

PCIEXT3

PCIEXC4,

PCIEXT4

PCIEXC5,

PCIEXT5

10, 11

12, 13

16, 17

Output

Differential output pairs. LVPECL interface levels.

FS1

BYPASS

V_CCA

Pulldown Frequency select pin. LVCMOS/LVTTL interface levels.

Pulldown Bypass select pin.

Input

Power

Input

Analog supply pin. Requires 24Ω series resistor.

PLL_BW

CLK

Pullup

Selects PLL Bandwidth input. LVCMOS/LVTTL interface levels.

Pulldown Non-inverting differential clock input.

Pullup/

nCLK

Input

Inverting differential clock input. V_CC/2 default when left floating.

Pulldown

FS0

Pullup Frequency select pin. LVCMOS/LVTTL interface levels.

PCIEXT0,

PCIEXC0

26, 27

Output

Differential output pairs. LVPECL interface levels.

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

TABLE 2. PIN CHARACTERISTICS

Symbol

C_IN

Parameter

Test Conditions

Minimum Typical

Maximum Units

Input Capacitance

Input Pullup Resistor

KΩ

R_PULLUP

R_PULLDOWNInput Pulldown Resistor

TABLE 3A. RATIO OF OUTPUT FREQUENCY TO

INPUT FREQUENCY FUNCTION TABLE, FS0

TABLE 3B. RATIO OF OUTPUT FREQUENCY TO

INPUT FREQUENCY FUNCTION TABLE, FS1

Inputs

Outputs

PCIEX1

5/4

Inputs

Outputs

PCIEX4

FS0

PCIEX0

PCIEX2

FS1

PCIEX3

PCIEX5

5/4

TABLE 3C. OUTPUT ENABLE

FUNCTION TABLE, nOE0

TABLE 3D. OUTPUT ENABLE

FUNCTION TABLE, nOE1

TABLE 3E. PLL BANDWIDTH TABLE

Inputs

Outputs

PCIEX0:2

Enabled

Inputs

Outputs

PCIEX3:5

Enabled

Bandwidth

PLL_BW

nOE0

nOE1

500kHz

1MHz

Disabled

9DB306BL

www.icst.com/products/hiperclocks.html

REV. A OCTOBER 22, 2004

123 4 5 6 7...15

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