Datasheet > 9763-11

9763-11

更新时间： 2024-02-21 04:47:56

品牌	Logo	应用领域
PSEMI		/
页数	文件大小	规格书
15页	289K
描述
3.2 GHz Delta-Sigma modulated Fractional-N Frequency Synthesizer for Low Phase Noise Applications

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技术参数
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9763-11 技术参数

生命周期：	Active	零件包装代码：	QFJ
包装说明：	QCCJ, LDCC68,1.0SQ	针数：	68
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.68	模拟集成电路 - 其他类型：	PLL FREQUENCY SYNTHESIZER
JESD-30 代码：	S-CQCC-J68	端子数量：	68
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	CERAMIC, METAL-SEALED COFIRED	封装代码：	QCCJ
封装等效代码：	LDCC68,1.0SQ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	电源：	3 V
认证状态：	Not Qualified	子类别：	PLL or Frequency Synthesis Circuits
标称供电电压 (Vsup)：	3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	J BEND	端子节距：	1.27 mm
端子位置：	QUAD	Base Number Matches：	1

9763-11 数据手册

Product Specification

PE9763

3.2 GHz Delta-Sigma modulated

Fractional-N Frequency Synthesizer

for Low Phase Noise Applications

Product Description

Peregrine’s PE9763 is a high performance fractional-N PLL

capable of frequency synthesis up to 3.2 GHz. The device is

designed for superior phase noise performance while providing

an order of magnitude reduction in current consumption, when

compared with the existing commercial space PLLs.

Features

• 3.2 GHz operation

• ÷10/11 dual modulus prescaler

• Selectable phase detector or charge

pump output

The PE9763 features a 10/11 dual modulus prescaler,

counters, a delta sigma modulator, a phase comparator and a

charge pump as shown in Figure 1. Counter values are

programmable through either a serial interface or directly hard-

wired.

• Serial or Direct mode access

• Frequency selectivity: Comparison

frequency / 2¹⁸

• Low power —- 25 - 30 mA at 3V (phase

detector / charge pump)

PE9763 is optimized for commercial space applications. Single

Event Latch up (SEL) is physically impossible and Single Event

Upset (SEU) is better than 10-9 errors per bit / day. Fabricated

in Peregrine’s patented UTSi® (Ultra Thin Silicon) CMOS

technology, the PE9763 offers excellent RF performance and

intrinsic radiation tolerance.

• Rad-Hard

• Ultra-low phase noise

• 68-lead CQFJ or Die

Figure 1. Block Diagram

F_in

Prescaler

10/11

Main

Counter

M_8:0

PD_U

A_3:0

R_5:0

PD_D

Pre_en

Secon-

dary

Phase

Detector

Charge

Pump

Primary

21-bit

Latch

20-bit

Latch

Sdata

Auxilia-

20-bit

Latch

DSM

f_r

R Counter

K_17:0

Direct

Document No. 70-0140-01 │ www.psemi.com

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