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93LC46T

更新时间： 2024-02-22 18:56:49
品牌 Logo 应用领域
美国微芯 - MICROCHIP 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
20页 321K
描述
1K/2K/4K 2.5V Microwire Serial EEPROM

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93LC46T 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Not Recommended零件包装代码：SOIC
包装说明：SOP, SOP8,.25针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.32.00.51Factory Lead Time：9 weeks
风险等级：5.24Is Samacsys：N
其他特性：3 WIRE INTERFACE; AUTOMATIC WRITE; ERAL AT 4.5V TO 6.0V备用内存宽度：8
最大时钟频率 (fCLK)：2 MHz数据保留时间-最小值：200
耐久性：1000000 Write/Erase CyclesJESD-30 代码：R-PDSO-G8
JESD-609代码：e3长度：4.9 mm
内存密度：1024 bit内存集成电路类型：EEPROM
内存宽度：16湿度敏感等级：3
功能数量：1端子数量：8
字数：64 words字数代码：64
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：64X16
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP8,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE并行/串行：SERIAL
峰值回流温度（摄氏度）：260电源：3/5 V
认证状态：Not Qualified座面最大高度：1.75 mm
串行总线类型：MICROWIRE最大待机电流：0.00003 A
子类别：EEPROMs最大压摆率：0.003 mA
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：2.5 V
标称供电电压 (Vsup)：3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：40宽度：3.9 mm
最长写入周期时间 (tWC)：10 ms写保护：SOFTWARE
Base Number Matches：1

93LC46T 数据手册

 浏览型号93LC46T的Datasheet PDF文件第3页浏览型号93LC46T的Datasheet PDF文件第4页浏览型号93LC46T的Datasheet PDF文件第5页浏览型号93LC46T的Datasheet PDF文件第7页浏览型号93LC46T的Datasheet PDF文件第8页浏览型号93LC46T的Datasheet PDF文件第9页 
93LC46/56/66  
After power-up, the device is automatically in the  
EWDS mode. Therefore, an EWEN instruction must be  
performed before any ERASE or WRITE instruction can  
be executed.  
2.0  
FUNCTIONAL DESCRIPTION  
When the ORG pin is connected to VCC, the (x16)  
organization is selected. When it is connected to  
ground, the (x8) organization is selected. Instruc-  
tions, addresses and write data are clocked into the  
DI pin on the rising edge of the clock (CLK). The DO  
pin is normally held in a high-Z state except when  
reading data from the device, or when checking the  
Ready/Busy status during a programming operation.  
The Ready/Busy status can be verified during an  
erase/write operation by polling the DO pin; DO low  
indicates that programming is still in progress, while  
DO high indicates the device is ready. The DO will  
enter the high-Z state on the falling edge of the CS.  
2.4  
Read  
The READ instruction outputs the serial data of the  
addressed memory location on the DO pin. A dummy  
zero bit precedes the 16-bit (x16 organization) or 8-bit  
(x8 organization) output string. The output data bits will  
toggle on the rising edge of the CLK and are stable  
after the specified time delay (TPD). Sequential read is  
possible when CS is held high. The memory data will  
automatically cycle to the next register and output  
sequentially.  
2.1  
Start Condition  
2.5  
Erase/Write Enable and Disable  
(EWEN, EWDS)  
The Start bit is detected by the device if CS and DI are  
both high with respect to the positive edge of CLK for  
the first time.  
The 93LC46/56/66 power up in the Erase/Write Disable  
(EWDS) state. All programming modes must be  
preceded by an Erase/Write Enable (EWEN) instruction.  
Once the EWEN instruction is executed, programming  
remains enabled until an EWDS instruction is executed  
or VCC is removed from the device. To protect against  
accidental data disturb, the EWDS instruction can be  
used to disable all erase/write functions and should  
follow all programming operations. Execution of a READ  
instruction is independent of both the EWEN and EWDS  
instructions.  
Before a Start condition is detected, CS, CLK and DI  
may change in any combination (except to that of a  
Start condition), without resulting in any device opera-  
tion (Read, Write, Erase, EWEN, EWDS, ERAL and  
WRAL). As soon as CS is high, the device is no longer  
in the Standby mode.  
An instruction following a Start condition will only be  
executed if the required amount of opcode, address  
and data bits for any particular instruction is clocked in.  
After execution of an instruction (i.e., clock in or out of  
the last required address or data bit) CLK and DI  
become “don't care” bits until a new Start condition is  
detected.  
2.6  
Erase  
The ERASE instruction forces all data bits of the speci-  
fied address to the logical “1” state. CS is brought low  
following the loading of the last address bit. This falling  
edge of the CS pin initiates the self-timed programming  
cycle.  
2.2  
Data In/Data Out (DI/DO)  
It is possible to connect the Data In and Data Out pins  
together. However, with this configuration it is possible  
for a “bus conflict” to occur during the “dummy zero”  
that precedes the read operation, if A0 is a logic high  
level. Under such a condition the voltage level seen at  
Data Out is undefined and will depend upon the relative  
impedances of Data Out and the signal source driving  
A0. The higher the current sourcing capability of A0,  
the higher the voltage at the Data Out pin.  
The DO pin indicates the Ready/Busy status of the  
device if CS is brought high after a minimum of 250 ns  
low (TCSL). DO at logical “0” indicates that program-  
ming is still in progress. DO at logical “1” indicates that  
the register at the specified address has been erased  
and the device is ready for another instruction.  
The erase cycle takes 4 ms per word typical.  
2.3  
Data Protection  
During power-up, all programming modes of operation  
are inhibited until VCC has reached a level greater than  
1.4V. During power-down, the source data protection  
circuitry acts to inhibit all programming modes when  
VCC has fallen below 1.4V at nominal conditions.  
The EWEN and EWDS commands give additional  
protection against accidentally programming during  
normal operation.  
DS21712C-page 6  
2002-2012 Microchip Technology Inc.  
1...3456789...20

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