89HPES8NT2ZABXG

更新时间： 2024-02-16 08:48:09

品牌	Logo	应用领域
艾迪悌 - IDT		开关 PC
页数	文件大小	规格书
3页	54K
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89HPES8NT2ZABXG 数据手册

IDT 89HPES8NT2 Product Brief

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Reliability, Availability, and Serviceability (RAS) Features

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Internal end-to-end parity protection on all TLPs ensures data integrity even in systems that do not implement end-to-end CRC (ECRC)

Supports ECRC pass-through

Supports Hot-Swap

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Power Management

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Supports PCI Power Management Interface specification, Revision 1.1 (PCI-PM)

Unused SerDes are disabled

Testability and Debug Features

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Built in SerDes Pseudo-Random Bit Stream (PRBS) generator

Ability to read and write any internal register via the SMBus

Ability to bypass link training and force any link into any mode

Provides statistics and performance counters

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Two SMBus Interfaces

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Slave interface provides full access to all software-visible registers by an external SMBus master

Master interface provides connection for an optional serial EEPROM used for initialization

Master interface is also used by an external Hot-Plug I/O expander

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Master and slave interfaces may be tied together so the switch can act as both master and slave

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Eight General Purpose Input/Output pins

Packaged in 19x19mm 324 ball BGA with 1mm ball spacing

Product Description

Utilizing standard PCI Express interconnect, the PES8NT2 provides the most efficient high-performance I/O connectivity solution for applications

requiring high throughput, low latency, and simple board layout with a minimum number of board layers. With support for non-transparent bridging, the

PES8NT2 is part of the IDT PCIe System Interconnect Products that target multi-host and intelligent I/O applications requiring inter-domain communi-

cation. The PES8NT2 provides 32 Gbps (4 GBps) of aggregated, full-duplex switching capacity through 8 integrated serial lanes, using proven and

robust IDT technology. Each lane provides 2.5 Gbps of bandwidth in both directions and is fully compliant with PCI Express Base specification 1.0a.

The PES8NT2 is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link, and Trans-

action layers in compliance with PCI Express Base specification Revision 1.0a. The PES8NT2 can operate either as a store and forward or cut-

through switch depending on the packet size and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and one

Virtual Channel (VC) with sophisticated resource management.

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March 14, 2007

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