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88P8342BHGI

更新时间： 2024-01-10 05:39:40
品牌 Logo 应用领域
艾迪悌 - IDT 外围集成电路
页数 文件大小 规格书
98页 669K
描述
Microprocessor Circuit, CMOS, PBGA820, GREEN, PLASTIC, BGA-820

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中文翻译

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88P8342BHGI 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：BGA
包装说明：GREEN, PLASTIC, BGA-820针数：820
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.82
JESD-30 代码：S-PBGA-B820JESD-609代码：e3
长度：35 mm端子数量：820
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA820,34X34,40封装形状：SQUARE
封装形式：GRID ARRAY峰值回流温度（摄氏度）：260
电源：1.8,3.3 V认证状态：Not Qualified
座面最大高度：2.44 mm子类别：Other Microprocessor ICs
最大供电电压：1.96 V最小供电电压：1.68 V
标称供电电压：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：MATTE TIN端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：30宽度：35 mm
uPs/uCs/外围集成电路类型：MICROPROCESSOR CIRCUITBase Number Matches：1

88P8342BHGI 数据手册

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SPI EXCHANGE 2 x SPI-3 TO SPI-4  
Issue1.0  
IDT88P8342  
- Number of errors  
- Number of bytes  
• Green parts available, see ordering information  
FEATURES  
• Functionality  
- Low speed to high speed SPI exchange device  
- Logical port (LP) mapping (SPI-3 <-> SPI-4) tables per direction  
- Per LP configurable memory allocation  
- Maskable interrupts for fatal errors  
APPLICATIONS  
• Ethernet transport  
• SONET / SDH packet transport line cards  
• Broadband aggregation  
• Multi-service switches  
- Fragment and burst length configurable per interface: min 16 bytes,  
max 256 bytes  
• Standard Interfaces  
• IP services equipment  
- Two OIF SPI-3: 8 or 32 bit, 19.44-133 MHz, 256 address range, 64  
concurrently active LPs per interface  
- One OIF SPI-4 phase 2: 80 - 400 MHz, 256 address range, 128  
concurrently active LPs  
- SPI-4 FIFO status channel options:  
• LVDS full-rate  
• LVTTL eighth-rate  
- Compatible with Network Processor Streaming Interface (NPSI)  
NPE-Framer mode of operation  
- SPI-4 ingress LVDS automatic bit alignment and lane de-skew over  
the entire frequency range  
- SPI-4 egress LVDS programmable lane pre-skew 0.1 to 0.3 cycle  
- IEEE 1149.1 JTAG  
- Serial or parallel microprocessor interface for control and monitoring  
Full Suite of Performance Monitoring Counters  
- Number of packets  
DESCRIPTION  
TheIDT88P8342isaSPI(SystemPacketInterface)ExchangewithtwoSPI-  
3 interfaces and one SPI-4 interface. The data that enter on the low speed  
interface (SPI-3) are mapped to logical identifiers (LIDs) and enqueued for  
transmissionoverthehighspeedinterface(SPI-4).Thedatathatenteronthe  
high speed interface (SPI-4) are mapped to logical identifiers (LIDs) and  
enqueued for transmission over a low speed interface (SPI-3). A data flow  
betweenSPI-3andSPI-4interfacesisaccomplishedwithLIDmaps.Thelogical  
port addresses and number of entries in the LID maps may be dynamically  
configured.Variousparametersofadataflowmaybeconfiguredbytheuser  
such as buffer memory size and watermarks. In a typical application, the  
IDT88P8342 enables connection of two SPI-3 devices to a SPI-4 network  
processor.InotherapplicationsaSPI-3orSPI-4devicemaybeconnectedto  
aSPI-3networkprocessorortrafficmanager.  
•
- Number of fragments  
FUNCTIONALBLOCKDIAGRAM  
SPI-3 to SPI-4 PFP  
SPI-3 A  
64 Logical Ports  
SPI-4 to SPI-3 PFP  
SPI-4  
128 Logical  
Ports  
SPI-3 to SPI-4 PFP  
SPI-4 to SPI-3 PFP  
SPI-3 B  
64 Logical Ports  
JTAG IF  
Uproc IF  
Clock Generator  
Control Path  
Data Path PFP = Packet Fragment Processor  
6371 drw01  
IDTandtheIDTlogoaretrademarksofIntegratedDeviceTechnology,Inc  
APRIL 2006  
INDUSTRIAL TEMPERATURE RANGE  
1
2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-6371/9  
1234567...98

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