Datasheet > 88C44-AF5-R

88C44-AF5-R

更新时间： 2024-01-26 13:32:31

品牌	Logo	应用领域
友顺 - UTC		/
页数	文件大小	规格书
16页	216K
描述
BUILT-IN DELAY CIRCUIT HIGH-PRECISION VOLTAGE DETECTOR

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88C44-AF5-R 技术参数

生命周期：	Active	零件包装代码：	SOT
包装说明：	LSSOP,	针数：	5
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.13
可调阈值：	NO	模拟集成电路 - 其他类型：	POWER SUPPLY SUPPORT CIRCUIT
JESD-30 代码：	R-PDSO-G5	长度：	2.9 mm
信道数量：	1	功能数量：	1
端子数量：	5	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	LSSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, LOW PROFILE, SHRINK PITCH	座面最大高度：	1.45 mm
最大供电电压 (Vsup)：	10 V	最小供电电压 (Vsup)：	0.95 V
标称供电电压 (Vsup)：	3.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	0.95 mm
端子位置：	DUAL	宽度：	1.6 mm
Base Number Matches：	1

88C44-AF5-R 数据手册

88CXX

CMOS IC

ꢀ

TECHNICAL TERMS

1. Detection voltage (-V_DET

)

The detection voltage -V_DETis the voltage at which the output switches to low. This detection voltage varies

slightly among products of the same type. The variation of voltages between the specified minimum [(-V_DET)min.]

and maximum [(-V_DET)max.] values is called the detection voltage range (See Figure 1).

Example: For the -V_DET=1.5V, detection voltage lies in the range of 1.470≦(-V_DET)≦1.530. This means that -V_DET

is 1.470 in a product while -V_DETis 1.530 in another of the same -V_DET=1.5V.

2. Release voltage (+V_DET

)

The release voltage +V_DETis the voltage at which the output returns (is “released”) to high. This release voltage

varies slightly among products of the same type. The variation of voltages between the specified minimum

[(+V_DET)min.] and maximum [(+V_DET)max.] values is called the release voltage range (See Figure 2).

Example: For the -V_DET=1.5V, the release voltage lies in the range of 1.514≦(+V_DET)≦1.652. This means that

+V_DETis 1.514 in a product while +V_DETis 1.652 in another of the same -V_DET=1.5V.

Remark: Although the detection voltage and release voltage overlap in the range of 1.514 V ~ 1.530 V, +V_DET

will always be larger than -V_DET

Release voltage

(+V^DET) Max.

Detection voltage

(-V^DET)Max.

(-V^DET)Min.

Voltage range Detection

Release voltage range

(+V^DET) Min.

OUT

Figure 1

3. Hysteresis width (V_HYS

Figure 2 (CD=0F)

)

The hysteresis width is the voltage difference between the detection voltage and the release voltage (B-A=V_HYSin

Figure 7). By giving a device hysteresis, trouble such as noise at the input is avoided.

4. Delay time (t_d)

The delay time is a time that the input voltage to V_DDterminal exceeds the release voltage (+V_DET) and then the

output of the OUT terminal inverts. The delay time can be changed by the additional external capacitor C_D.

UNISONIC TECHNOLOGIES CO., LTD

www.unisonic.com.tw

QW-R502-040,A

1...4 5 678 9 10...16

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