SMPS Stacked MLC Capacitors
(SM Style) Technical Information on SMPS Capacitors
ELECTRICAL SPECIFICATIONS
Temperature Coefficient
Dielectric Withstanding Voltage 25°C (Flash Test)
C0G and X7R: 1ꢂ05 rated voltage for ꢂ seconds with ꢂ0 mA max
charging current. (ꢂ00 ꢄolt units @ 7ꢂ0 ꢄDC)
ZꢂU: 1005 rated voltage for ꢂ seconds with ꢂ0 mA max charging
current.
C0G: A Temperature Coefficient - 0 ±±0 ppmꢀ/Cꢁ -ꢂꢂ/ to ꢃ+1ꢂ/C
X7R: C Temperature Coefficient - ±+ꢂ5ꢁ -ꢂꢂ/ to ꢃ+1ꢂ/C
ZꢂU: E Temperature Coefficient - ꢃ11ꢁ -ꢂ65ꢁ ꢃ+0/ to ꢃ8ꢂ/C
Capacitance Test (MIL-STD-101 Method ±0ꢂ)
C0G: 1ꢂ/Cꢁ +.0±0.1 ꢄrms (open circuit voltage) at +KHz
X7R: 1ꢂ/Cꢁ +.0±0.1 ꢄrms (open circuit voltage) at +KHz
ZꢂU: 1ꢂ/Cꢁ 0.ꢂ ꢄrms max (open circuit voltage) at +KHz
Life Test (+000 hrs)
C0G and X7R: 1005 rated voltage at ꢃ+1ꢂ/C. (ꢂ00 ꢄolt units @
600 ꢄDC)
ZꢂU: +ꢂ05 rated voltage at ꢃ8ꢂ/C
Dissipation Factor 25°C
C0G: 0.+ꢂ5 Max @ 1ꢂ/Cꢁ +.0±0.1 ꢄrms (open circuit voltage) at +KHz
X7R: 1.ꢂ5 Max @ 1ꢂ/Cꢁ +.0±0.1 ꢄrms (open circuit voltage) at +KHz
ZꢂU: ±.05 Max @ 1ꢂ/Cꢁ 0.ꢂ ꢄrms max (open circuit voltage) at +KHz
Moisture Resistance (MIL-STD-101 Method +06)
C0Gꢁ X7Rꢁ ZꢂU: Ten cycles with no voltage applied.
Thermal Shock (MIL-STD-101 Method +07ꢁ Condition A)
Immersion Cycling (MIL-STD-101 Method +04ꢁ Condition B)
Insulation Resistance 25°C (MIL-STD-101 Method ±01)
C0G and X7R: +00K MΩ or +000 MΩ-µFꢁ whichever is less.
ZꢂU: +0K MΩ or +000 MΩ-µFꢁ whichever is less.
Resistance To Solder Heat (MIL-STD-101ꢁ Method 1+0ꢁ
Condition Bꢁ for 10 seconds)
Insulation Resistance 125°C (MIL-STD-101 Method ±01)
C0G and X7R: +0K MΩ or +00 MΩ-µFꢁ whichever is less.
ZꢂU: +K MΩ or +00 MΩ-µFꢁ whichever is less.
Typical ESR Performance (mΩ)
Aluminum
Electrolytic
100µF/50V
±00
Low ESR
Solid Aluminum
MLCC
MLCC
Solid Tantalum
100µF/10V
Electrolytic
100µF/16V
SMPS
100µF/50V
SMPS
4.7µF/50V
ESR @ +0KHz
ESR @ ꢂ0KHz
ESR @ +00KHz
ESR @ ꢂ00KHz
ESR @ +MHz
ESR @ ꢂMHz
ESR @ +0MHz
71
67
61
ꢂ6
ꢂ6
71
9+
19
11
10
+8
+7
+7
11
±
1
1.ꢂ
4
7
+1.ꢂ
10
66
1±
+ꢂ
8
7.ꢂ
8
18ꢂ
180
16ꢂ
16ꢂ
±±ꢂ
ꢂ60
+4
HOW TO ORDER
AVX Styles: SM-1, SM-2, SM-3, SM-4, SM-5, SM-6
SM0
1
7
C
106
M
A
N
650
AVX Style
Size
Voltage Temperature
Capacitance
Code
(1 significant digits
ꢃ number of zeros)
+0 pF = +00
+00 pF = +0+
+ꢁ000 pF = +01
11ꢁ000 pF = 11±
110ꢁ000 pF = 114
+µF = +0ꢂ
Capacitance
Tolerance
C0G:
Test Level
A = Standard
B = Hi-Rel*
Termination
N = Straight Lead
J = Leads formed in
L = Leads formed out
P = P Style Leads
Z = Z Style Leads
Height
Max
SM0 = Uncoated
See
ꢂ0ꢄ = ꢂ Coefficient
SMꢂ = Epoxy Coated Dimensions +00ꢄ = +
C0G = A
X7R = C
ZꢂU = E
Dimension “A”
+10 = 0.+10"
140 = 0.140"
±60 = 0.±60"
480 = 0.480"
6ꢂ0 = 0.6ꢂ0"
chart
100ꢄ = 1
ꢂ00ꢄ = 7
J = ±ꢂ5
K = ±+05
M = ±105
X7R:
K = ±+05
M = ±105
Z = ꢃ805ꢁ -105
+0 µF = +06
+00 µF = +07
ZꢂU:
M = ±105
Z = ꢃ805ꢁ -105
P = GMꢄ (ꢃ+00ꢁ -05)
Note: Capacitors with X7R and ZꢂU dielectrics are not intended for applications
across AC supply mains or AC line filtering with polarity reversal. Contact plant
for recommendations.
Hi-Rel screening for C0G and X7R only. Screening consists of +005 Group A
*
(B Level)ꢁ Subgroup + per MIL-PRF-49470.
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