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87C575 PDF预览

87C575

更新时间: 2022-12-11 19:23:06
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
40页 386K
描述
80C51 8-bit microcontroller family 8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

87C575 数据手册

 浏览型号87C575的Datasheet PDF文件第3页浏览型号87C575的Datasheet PDF文件第4页浏览型号87C575的Datasheet PDF文件第5页浏览型号87C575的Datasheet PDF文件第7页浏览型号87C575的Datasheet PDF文件第8页浏览型号87C575的Datasheet PDF文件第9页 
Philips Semiconductors  
Product specification  
80C51 8-bit microcontroller family  
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer  
80C575/83C575/  
87C575  
PIN DESCRIPTIONS (Continued)  
PIN NUMBER  
MNEMONIC  
DIP  
LCC  
QFP TYPE NAME AND FUNCTION  
Port 3: (continued)  
10  
11  
12  
13  
14  
11  
13  
14  
15  
16  
5
7
8
9
10  
I
O
I
I
I
P3.0 RxD  
P3.1 TxD  
P3.2 INT0  
P3.3 INT1  
P3.4 T0  
Serial receive port  
Serial transmit port enabled only when transmitting serial data  
External interrupt 0  
External interrupt 1  
Timer/counter 0 input  
CMPR- Common - reference to comparators 1, 2, 3  
15  
16  
17  
17  
18  
19  
11  
12  
13  
I
P3.5 T1  
Timer/counter 1 input  
CMP1+ Comparator 1 positive input  
P3.6 WR  
CMP2+ Comparator 2 positive input  
P3.7 RD  
O
O
External data memory write strobe  
External data memory read strobe  
CMP3+ Comparator 3 positive input  
RST  
9
10  
4
I
Reset: A low on this pin asynchronously resets all port pins to a low state except P3.1. The  
pin must be held low with the oscillator running for 24 oscillator cycles to initialize the  
internal registers. An internal diffused resistor to V permits a power on reset using only  
CC  
an external capacitor to V . RST has a Schmitt trigger input stage to provide additional  
SS  
noise immunity with a slow rising input voltage.  
ALE/PROG  
30  
33  
27  
I/O  
Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the  
address during an access to external memory. In normal operation, ALE is emitted at a  
constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking.  
Note that one ALE pulse is skipped during each access to external data memory. ALE is  
switched off if the bit 0 in the AUXR register (8EH) is set. This pin is also the program pulse  
input (PROG) during EPROM programming.  
PSEN  
29  
31  
32  
35  
26  
29  
O
I
Program Store Enable: The read strobe to external program memory. When the device is  
executing code from the external program memory, PSEN is activated twice each machine  
cycle, except that two PSEN activations are skipped during each access to external data  
memory. PSEN is not activated during fetches from internal program memory.  
EA/V  
External Access Enable/Programming Supply Voltage: EA must be externally held low  
to enable the device to fetch code from external program memory locations 0000H to  
1FFFH. If EA is held high, the device executes from internal program memory unless the  
program counter contains an address greater than 1FFFH. This pin also receives the  
PP  
12.75V programming supply voltage (V ) during EPROM programming.  
PP  
XTAL1  
XTAL2  
19  
18  
21  
20  
15  
14  
I
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator  
circuits.  
O
Crystal 2: Output from the inverting oscillator amplifier.  
6
1998 May 01  

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