Datasheet > 8536AGI-33T

8536AGI-33T

更新时间： 2024-01-17 09:36:40

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
15页	603K
描述
Clock Generator

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中文翻译

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技术参数
数据手册

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8536AGI-33T 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
Reach Compliance Code：	unknown	风险等级：	5.92
Base Number Matches：	1

8536AGI-33T 数据手册

PRELIMINARY

ICS8536I-33

Integrated

Circuit

Systems, Inc.

LOW SKEW, 1-TO-6, CRYSTAL OSCILLATOR/

LVCMOS-TO-3.3V LVPECL/LVCMOS FANOUT BUFFER

TERMINATION FOR LVPECL OUTPUTS

designed to drive 50Ω transmission lines. Matched imped-

ance techniques should be used to maximize operating

frequency and minimize signal distortion. Figures 3A and

3B show two different layouts which are recommended

only as guidelines. Other suitable clock layouts may exist

and it would be recommended that the board designers

simulate to guarantee compatibility across all printed cir-

cuit and clock component process variations.

The clock layout topology shown below is a typical termi-

nation for LVPECL outputs. The two different layouts men-

tioned are recommended only as guidelines.

FOUT and nFOUT are low impedance follower outputs that

generate ECL/LVPECL compatible outputs. Therefore, ter-

minating resistors (DC current path to ground) or current

sources must be used for functionality. These outputs are

3.3V

_o= 50Ω

125Ω

FOUT

FIN

Z_o= 50Ω

FOUT

FIN

50Ω

V_CC- 2V

RTT =

Z_o

RTT

((V_OH+ V_OL) / (V_CC– 2)) – 2

84Ω

FIGURE 3A. LVPECL OUTPUTTERMINATION

FIGURE 3B. LVPECL OUTPUTT ERMINATION

8536AGI-33

www.icst.com/products/hiperclocks.html

REV.A MARCH 16, 2006

1...7 8 91011 12 13...15

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