5秒后页面跳转
8533AGI-31 PDF预览

8533AGI-31

更新时间: 2024-01-12 19:37:00
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
16页 966K
描述
Clock Generator

8533AGI-31 技术参数

是否Rohs认证: 符合生命周期:Obsolete
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.81
Base Number Matches:1

8533AGI-31 数据手册

 浏览型号8533AGI-31的Datasheet PDF文件第5页浏览型号8533AGI-31的Datasheet PDF文件第6页浏览型号8533AGI-31的Datasheet PDF文件第7页浏览型号8533AGI-31的Datasheet PDF文件第9页浏览型号8533AGI-31的Datasheet PDF文件第10页浏览型号8533AGI-31的Datasheet PDF文件第11页 
ICS8533I-31  
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/DIFFERENTIAL-TO- 3.3V LVPECL FANOUT BUFFER  
PRELIMINARY  
Application Information  
Recommendations for Unused Input and Output Pins  
Inputs:  
Outputs:  
LVCMOS Control Pins  
LVPECL OUTPUTS  
All control pins have internal pull-ups; additional resistance is not  
required but can be added for additional protection. A 1kresistor  
can be used.  
All unused LVPECL outputs can be left floating. We recommend  
that there is no trace attached. Both sides of the differential output  
pair should either be left floating or terminated.  
CLK/nCLK Inputs  
For applications not requiring the use of the differential input, both  
CLK and nCLK can be left floating. Though not required, but for  
additional protection, a 1kresistor can be tied from CLK to  
ground.  
Crystal Inputs  
For applications not requiring the use of the crystal oscillator input,  
both XTAL_IN and XTAL_OUT can be left floating. Though not  
required, but for additional protection, a 1kresistor can be tied  
from XTAL_IN to ground.  
Wiring the Differential Input to Accept Single-Ended Levels  
Figure 2 shows how the differential input can be wired to accept  
single-ended levels. The reference voltage V_REF = VCC/2 is  
generated by the bias resistors R1, R2 and C1. This bias circuit  
should be located as close as possible to the input pin. The ratio of  
R1 and R2 might need to be adjusted to position the V_REF in the  
center of the input voltage swing. For example, if the input clock  
swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and  
VDD  
R1  
1K  
Single Ended Clock Input  
R2/R1 = 0.609.  
CLK  
V_REF  
nCLK  
C1  
0.1u  
R2  
1K  
Figure 2. Single-Ended Signal Driving Differential Input  
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER  
8
ICS8533AGI-31 REV. A DECEMBER 13, 2007  

与8533AGI-31相关器件

型号 品牌 获取价格 描述 数据表
8533AGI-31LF IDT

获取价格

Clock Generator
8533AGI-31LFT IDT

获取价格

Clock Generator
8533AGI-31T IDT

获取价格

Clock Generator
8533I-01 RENESAS

获取价格

Low Skew,1-to-4 Differential-to-3.3V LVPECL Fanout Buffer
8533J80CBE2 ITT

获取价格

Pushbutton Switch, SPST, On-(off), Vertical, 2 PCB Hole Cnt, Solder Terminal, Through Hole
8533J80CBE3 ITT

获取价格

Pushbutton Switch, SPST, On-(off), Vertical, 2 PCB Hole Cnt, Solder Terminal, Through Hole
8533J80CQE3 ITT

获取价格

Pushbutton Switch, SPST, On-(off), Vertical, 1A, 28VDC, 2 PCB Hole Cnt, Solder Terminal, T
8533J80ZGE11 ITT

获取价格

Pushbutton Switch, SPST, On-(off), Vertical, 1A, 28VDC, Wire Terminal
8533J80ZQE2 ITT

获取价格

Pushbutton Switch, SPST, On-(off), Vertical, 1A, 28VDC, Solder Lug Terminal, Panel Mount
8533J81CGE22 ITT

获取价格

Switch, SPST, Vertical, 1A, 28VDC, Through Hole-straight,