Datasheet > 8442AY

8442AY

更新时间： 2024-01-28 10:35:06

品牌	Logo	应用领域
艾迪悌 - IDT		时钟外围集成电路晶体
页数	文件大小	规格书
16页	876K
描述
Clock Generator, 700MHz, PQFP32, 7 X 7 MM, 1.4 MM HEIGHT, MS-026BBA, LQFP-32

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8442AY 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	7 X 7 MM, 1.4 MM HEIGHT, MS-026BBA, LQFP-32	针数：	32
Reach Compliance Code：	not_compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.76
JESD-30 代码：	S-PQFP-G32	JESD-609代码：	e0
长度：	7 mm	湿度敏感等级：	3
端子数量：	32	最高工作温度：	85 °C
最低工作温度：		最大输出时钟频率：	700 MHz
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装等效代码：	QFP32,.35SQ,32	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE	峰值回流温度（摄氏度）：	240
电源：	3.3 V	主时钟/晶体标称频率：	25 MHz
认证状态：	Not Qualified	座面最大高度：	1.6 mm
子类别：	Clock Generators	最大供电电压：	3.465 V
最小供电电压：	3.135 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	OTHER	端子面层：	Tin/Lead (Sn85Pb15)
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	20
宽度：	7 mm	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER
Base Number Matches：	1

8442AY 数据手册

ICS8442

Integrated

Circuit

ICS8442

700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL

700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER

TSD

Systems, Inc.

LVDS FREQUENCY SYNTHESIZER

FUNCTIONAL DESCRIPTION

cific default state that will automatically occur during power-

NOTE: The functional description that follows describes op-

eration using a 25MHz crystal. Valid PLL loop divider values

for different crystal or input frequencies are defined in the In-

put Frequency Characteristics, Table 5, NOTE 1.

up. The TEST output is LOW when operating in the parallel

input mode.The relationship between the VCO frequency, the

crystal frequency and the M divider is defined as follows:

fVCO = fxtal x M

The ICS8442 features a fully integrated PLL and therefore

requires no external components for setting the loop band-

width. A fundamental crystal is used as the input to the on-

chip oscillator.The output of the oscillator is fed into the phase

detector. A 25MHz crystal provides a 25MHz phase detector

reference frequency. The VCO of the PLL operates over a

range of 250MHz to 700MHz. The output of the M divider is

also applied to the phase detector.

The M value and the required values of M0 through M8 are

shown in Table 3B, Programmable VCO Frequency Function

Table.Valid M values for which the PLL will achieve lock for a

25MHz reference are defined as 10 ≤ M ≤ 28. The frequency

out is defined as follows:

FOUT = fVCO = fxtal x M

Serial operation occurs when nP_LOAD is HIGH and S_LOAD

is LOW. The shift register is loaded by sampling the S_DATA

bits with the rising edge of S_CLOCK. The contents of the

shift register are loaded into the M divider and N output di-

vider when S_LOAD transitions from LOW-to-HIGH. The M

divide and N output divide values are latched on the HIGH-to-

LOW transition of S_LOAD. If S_LOAD is held HIGH, data at

the S_DATA input is passed directly to the M divider and N

output divider on each rising edge of S_CLOCK. The serial

mode can be used to program the M and N bits and test bits

T1 and T0.The internal registersT0 and T1 determine the state

of the TEST output as follows:

The phase detector and the M divider force the VCO output fre-

quency to be M times the reference frequency by adjusting the

VCO control voltage. Note that for some values of M (either too

high or too low), the PLL will not achieve lock.The output of the

VCO is scaled by a divider prior to being sent to each of the

LVDS output buffers.The divider provides a 50% output duty cycle.

The programmable features of the ICS8442 support two input

modes to program the M divider and N output divider.The two

input operational modes are parallel and serial. Figure 1 shows

the timing diagram for each mode. In parallel mode, the

nP_LOAD input is initially LOW.The data on inputs M0 through

M8 and N0 and N1 is passed directly to the M divider and

N output divider. On the LOW-to-HIGH transition of the

nP_LOAD input, the data is latched and the M divider remains

loaded until the next LOW transition on nP_LOAD or until a

serial event occurs. As a result, the M and N bits can be

hardwired to set the M divider and N output divider to a spe-

T1 T0

TEST Output

LOW

S_Data, Shift Register Input

Output of M divider

CMOS FOUT

ERIAL LOADING

S_CLOCK

S_DATA

*NULL N1

N0 M8

M5 M4

M3 M2

S_LOAD

nP_LOAD

PARALLEL LOADING

M0:M8, N0:N1

nP_LOAD

M, N

S_LOAD

Time

FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS

*NOTE: The NULL timing slot must be observed.

8442AY

www.icst.com/products/hiperclocks.html

REV. D MAY 10, 2005

IDT™ / ICS™ 700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER

ICS8442

123 4 5 6 7...16

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与8442AY相关器件

型号	品牌	描述	获取价格	数据表
8442AYT	IDT	Clock Generator, 700MHz, PQFP32, 7 X 7 MM, 1.4 MM HEIGHT, MS-026BBA, LQFP-32	获取价格
8442BYILF	IDT	CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS	获取价格
8442BYILFT	IDT	CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS	获取价格
8442BYLF	IDT	CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS	获取价格
8442BYLFT	IDT	CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS	获取价格
844308-1	TE	CRIMPER, WIRE .120 F	获取价格

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