Datasheet > 84329BM-01LF

84329BM-01LF

更新时间： 2024-01-16 08:04:12

品牌	Logo	应用领域
艾迪悌 - IDT		时钟光电二极管外围集成电路晶体
页数	文件大小	规格书
21页	314K
描述
SOIC-28, Tube

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84329BM-01LF 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	7.50 X 18.05 MM, 2.25 MM HEIGHT, ROHS COMPLIANT, MS-013, MO-119, SOIC-28	针数：	28
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.84
Is Samacsys：	N	JESD-30 代码：	R-PDSO-G28
JESD-609代码：	e3	长度：	18.05 mm
湿度敏感等级：	1	端子数量：	28
最高工作温度：	70 °C	最低工作温度：
最大输出时钟频率：	700 MHz	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP28,.4
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260	电源：	3.3 V
主时钟/晶体标称频率：	25 MHz	认证状态：	Not Qualified
座面最大高度：	2.65 mm	子类别：	Clock Generators
最大压摆率：	125 mA	最大供电电压：	3.465 V
最小供电电压：	3.135 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Matte Tin (Sn) - annealed
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.5 mm	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER
Base Number Matches：	1

84329BM-01LF 数据手册

ICS84329B-01

700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

Functional Description

NOTE: The functional description that follows describes operation

using a 16MHz crystal. Valid PLL loop divider values for different

crystal or input frequencies are defined in the Input Frequency

Characteristics, Table 6, NOTE 1.

nP_LOAD input is LOW. The data on inputs M0 through M8 and N0

through N1 is passed directly to the M divider and N output divider.

On the LOW-to-HIGH transition of the nP_LOAD input, the data is

latched and the M divider remains loaded until the next LOW

transition on nP_LOAD or until a serial event occurs. The TEST

output is Mode 000 (shift register out) when operating in the

parallel input mode. The relationship between the VCO frequency,

the crystal frequency and the M divider is defined as follows:

fVCO = fXTAL x M

The ICS84329B-01 features a fully integrated PLL and therefore

requires no external components for setting the loop bandwidth. A

parallel resonant, fundamental crystal is used as the input to the

on-chip oscillator. The output of the oscillator is divided by 16 prior

to the phase detector. With a 16MHz crystal this provides a 1MHz

reference frequency. The VCO of the PLL operates over a range

of 250MHz to 700MHz. The output of the M divider is also applied

to the phase detector.

The M value and the required values of M0 through M8 are shown

in Table 3B, Programmable VCO Frequency Function Table. Valid

M values for which the PLL will achieve lock are defined as

250  M 511. The frequency out is defined as follows:

fout = fVCO = fXTAL x M

The phase detector and the M divider force the VCO output

frequency to be M times the reference frequency ÷ 16 by adjusting

the VCO control voltage. Note that for some values of M (either too

high or too low), the PLL will not achieve lock. The output of the

VCO is scaled by a divider prior to being sent to each of the

LVPECL output buffers. The divider provides a 50% output duty

cycle.

Serial operation occurs when nP_LOAD is HIGH and S_LOAD is

LOW. The shift register is loaded by sampling the S_DATA bits with

the rising edge of S_CLOCK. The contents of the shift register are

loaded into the M divider when S_LOAD transitions from

LOW-to-HIGH. The M divide and N output divide values are

latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is

held HIGH, data at the S_DATA input is passed directly to the M

divider on each rising edge of S_CLOCK. The serial mode can be

used to program the M and N bits and test bits T2:T0. The internal

resistors T2:T0 determine the state of the TEST output as follows:

The programmable features of the ICS84329B-01 support two

input modes to program the M divider and N output divider.

The two input operational modes are parallel and serial. Figure 1

shows the timing diagram for each mode. In parallel mode the

TEST Output

fOUT

Shift Register Out

HIGH

PLL Reference XTAL ÷16

(VCO ÷ M) /2 (non 50% Duty Cycle M Divider)

fOUT, LVCMOS Output Frequency < 200MHz

LOW

fOUT

S_CLOCK ÷ M (non 50% Duty Cycle M Divider)

fOUT ÷ 4

S_CLOCK ÷ N Divider

fOUT

SERIAL LOADING

S_CLOCK

T2 T1 T0 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0

S_DATA

S_LOAD

nP_LOAD

PARALLEL LOADING

M, N

M0:M8, N0:N1

nP_LOAD

Time

Figure 1. Parallel & Serial Load Operations

IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER

ICS84329BM-01 REV. C AUGUST 19, 2013

123 4 5 6 7...21

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与84329BM-01LF相关器件

型号	品牌	描述	获取价格	数据表
84329BM-01LFT	IDT	SOIC-28, Reel	获取价格
84329BM-01T	IDT	Clock Generator, 700MHz, PDSO28, 7.50 X 18.05 MM, 2.25 MM HEIGHT, MS-013, MO-119, SOIC-28	获取价格
84329BV	IDT	Clock Generator, 700MHz, PQCC28, 11.50 X 11.50 MM, 3.90 MM HEIGHT, PLASTIC, MS-018, LCC-28	获取价格
84329BV-01	IDT	Clock Generator, 700MHz, PQCC28, 11.60 X 11.40 MM, 4.10 MM HEIGHT, PLASTIC, MS-018, LCC-28	获取价格
84329BV-01LF	IDT	Clock Generator, 700MHz, PQCC28, 11.60 X 11.40 MM, 4.10 MM HEIGHT, PLASTIC, MS-018, LCC-28	获取价格
84329BV-01LFT	IDT	Clock Generator, 700MHz, PQCC28, 11.60 X 11.40 MM, 4.10 MM HEIGHT, PLASTIC, MS-018, LCC-28	获取价格

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