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84329AV-01T

更新时间： 2024-01-01 06:48:37

品牌	Logo	应用领域
艾迪悌 - IDT		晶体时钟发生器微控制器和处理器外围集成电路
页数	文件大小	规格书
20页	334K
描述
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

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84329AV-01T 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	LCC	包装说明：	11.60 X 11.40 MM, 4.10 MM HEIGHT, PLASTIC, MS-018, LCC-28
针数：	28	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.91	Is Samacsys：	N
JESD-30 代码：	S-PQCC-J28	JESD-609代码：	e0
长度：	11.505 mm	湿度敏感等级：	1
端子数量：	28	最高工作温度：	70 °C
最低工作温度：		最大输出时钟频率：	700 MHz
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装等效代码：	LDCC28,.5SQ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	峰值回流温度（摄氏度）：	225
电源：	3.3 V	主时钟/晶体标称频率：	25 MHz
认证状态：	Not Qualified	座面最大高度：	4.57 mm
子类别：	Clock Generators	最大压摆率：	110 mA
最大供电电压：	3.465 V	最小供电电压：	3.135 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn85Pb15)	端子形式：	J BEND
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	11.505 mm
uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER	Base Number Matches：	1

84329AV-01T 数据手册

ICS84329-01

700MHZ, LOW JITTER, CRYSTAL-TO-3.3V

DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

FUNCTIONAL DESCRIPTION

NOTE: The functional description that follows describes to the M divider and N output divider. On the LOW-to-HIGH

operation using a 16MHz crystal. Valid PLL loop divider transition of the nP_LOAD input, the data is latched and the

values for different crystal or input frequencies are defined M divider remains loaded until the next LOW transition on

in the Input Frequency Characteristics, Table 6, NOTE 1.

nP_LOAD or until a serial event occurs. The TEST output is

Mode 000 (shift register out) when operating in the parallel

input mode. The relationship between the VCO frequency,

the crystal frequency and the M divider is defined as fol-

The ICS84329-01 features a fully integrated PLL and there-

fore requires no external components for setting the loop

bandwidth. A series-resonant, fundamental crystal is used

as the input to the on-chip oscillator. The output of the oscil-

lator is divided by 16 prior to the phase detector. With a

16MHz crystal this provides a 1MHz reference frequency.

The VCO of the PLL operates over a range of 200MHz to

700MHz. The output of the M divider is also applied to the

phase detector.

lows:

fxtal

fVCO =

The M value and the required values of M0 through M8 are

shown in Table 3B, Programmable VCO Frequency Func-

tion Table. Valid M values for which the PLL will achieve

lock are defined as 200 ≤ M ≤ 511. The frequency out is

defined as follows:

fVCO fxtal

fout

The phase detector and the M divider force the VCO output

frequency to be M times the reference frequency ÷ 16 by

adjusting the VCO control voltage. Note that for some values

of M (either too high or too low), the PLL will not achieve lock.

The output of the VCO is scaled by a divider prior to being

sent to each of the LVPECL output buffers. The divider pro-

vides a 50% output duty cycle.

Serial operation occurs when nP_LOAD is HIGH and

S_LOAD is LOW. The shift register is loaded by sampling

the S_DATA bits with the rising edge of S_CLOCK. The con-

tents of the shift register are loaded into the M divider when

S_LOAD transitions from LOW-to-HIGH. The M divide and

N output divide values are latched on the HIGH-to-LOW

transition of S_LOAD. If S_LOAD is held HIGH, data at the

S_DATA input is passed directly to the M divider on each

rising edge of S_CLOCK. The serial mode can be used to

program the M and N bits and test bits T2:T0. The internal

registers T2:T0 determine the state of the TEST output as

follows:

The programmable features of the ICS84329-01 support

two input modes to program the M divider and N output

divider. The two input operational modes are parallel and

serial. Figure 1 shows the timing diagram for each mode. In

parallel mode the nP_LOAD input is LOW. The data on in-

puts M0 through M8 and N0 through N1 is passed directly

TEST Output

Shift Register Out

fOUT

High

PLL Reference Xtal ÷ 16

VCO ÷ M (non 50% Duty M divider)

fOUT

LVCMOS Output Frequency < 200MHz

Low

S_CLOCK ÷ M

(non 50% Duty Cycle M divider)

S_CLOCK ÷ N divider

fOUT

fOUT ÷ 4

SERIAL LOADING

S_CLOCK

S_DATA

S_LOAD

nP_LOAD

M8 M7 M6 M5 M4 M3 M2 M1 M0

PARALLEL LOADING

M, N

M0:M8, N0:N1

nP_LOAD

S_LOAD

Time

FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS

www.idt.com

84329AM-01

REV. D AUGUST 7, 2010

123 4 5 6 7...20

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