Datasheet > 83918

83918

更新时间： 2024-01-24 06:17:39

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
19页	332K
描述
Low Skew, 1:18 Crystal-to-LVCMOS/LVTTL Fanout Buffer

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83918 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	QFP
包装说明：	LQFP, QFP32,.35SQ,32	针数：	32
Reach Compliance Code：	not_compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.33
JESD-30 代码：	S-PQFP-G32	JESD-609代码：	e0
长度：	7 mm	湿度敏感等级：	3
端子数量：	32	最高工作温度：	85 °C
最低工作温度：	-40 °C	最大输出时钟频率：	250 MHz
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装等效代码：	QFP32,.35SQ,32	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE	峰值回流温度（摄氏度）：	240
电源：	3.3 V	主时钟/晶体标称频率：	40 MHz
认证状态：	Not Qualified	座面最大高度：	1.6 mm
子类别：	Clock Generators	最大压摆率：	24 mA
最大供电电压：	3.465 V	最小供电电压：	3.135 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn85Pb15)	端子形式：	GULL WING
端子节距：	0.8 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	20	宽度：	7 mm
uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER	Base Number Matches：	1

83918 数据手册

83918 Data Sheet

Table 5B. AC Characteristics, V_DD= 3.3V 5%,V_DDO= 2.5V 5%, T_A= -40°C to 85°C

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

f_OUT

Output Frequency

200

MHz

Propagation Delay, Low to High;

NOTE 1

tp_LH

tjit(Ø)

tjit

RMS Phase Jitter, (Random);

NOTE 2

25MHz,

0.465

0.161

Integration Range: 1kHz to 1MHz

Additive Phase Jitter, RMS; refer

to Additive Phase Jitter Section

155.52MHz,

Integration Range: 12kHz to 20MHz

tsk(o)

tsk(pp)

t_R/ t_F

odc

Output Skew; NOTE 3, 6

Part-to-Part Skew; NOTE 4, 6

Output Rise/Fall Time; NOTE 5

Output Duty Cycle

20% to 80%

300

700

_OUT 150MHz

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

All parameters measured at f_OUTunless noted otherwise.

NOTE 1: Measured from V_DD/2 of the input to V_DDO/2 of the output.

NOTE 2: Refer to the Phase Noise Plot following this section.

NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V_DDO/2.

NOTE 4: Defined as the skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature

and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V_DDO/2.

NOTE 5: These parameters are guaranteed by characterization. Not tested in production.

NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.

Table 5C. AC Characteristics, V_DD= 3.3V 5%,V_DDO= 1.8V 0.2V, T_A= -40°C to 85°C

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

f_OUT

Output Frequency

200

MHz

Propagation Delay, Low to High;

NOTE 1

tp_LH

tjit(Ø)

tjit

1.65

4.3

RMS Phase Jitter, (Random);

NOTE 2

25MHz,

0.595

0.228

Integration Range: 1kHz to 1MHz

Additive Phase Jitter, RMS; refer

to Additive Phase Jitter Section

155.52MHz,

Integration Range: 12kHz to 20MHz

tsk(o)

tsk(pp)

t_R/ t_F

odc

Output Skew; NOTE 3, 6

Part-to-Part Skew; NOTE 4, 6

Output Rise/Fall Time; NOTE 5

Output Duty Cycle

20% to 80%

200

800

_OUT 150MHz

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

All parameters measured at f_OUTunless noted otherwise.

NOTE 1: Measured from V_DD/2 of the input to V_DDO/2 of the output.

NOTE 2: Refer to the Phase Noise Plot following this section.

NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V_DDO/2.

NOTE 4: Defined as the skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature

and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V_DDO/2.

NOTE 5: These parameters are guaranteed by characterization. Not tested in production.

NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.

Revision B March 17, 2016

1...3 4 567 8 9...19

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