Datasheet > 82V3399

82V3399

更新时间： 2022-02-26 12:26:01

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
5页	59K
描述
Synchronization Management WAN PLL and Clock Generatiion for IEEE-1588

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数据手册

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82V3399 数据手册

82V3399 SHORT FORM DATA SHEET

FUNCTIONAL BLOCK DIAGRAM

OUT1

MUX

Divider

OUT1

OUT2

MUX

OUT2

OUT3

APLL

MUX

T4 Input

OUT3

MUX

T4 APLL

T4 DPLL

Selector

Input

Input Pre-Divider

Priority

IN1

IN2

IN3

IN4

IN5

IN6

OUT4

MUX

Divider

OUT4

Monitors

EX_SYNC1

EX_SYNC2

Selection

OUT5_POS

OUT5_NEG

OUT5

MUX

Divider

APLL

MUX

T0 Input

Selector

T0 APLL

T0 DPLL

OUT6_POS

OUT6_NEG

OUT6

MUX

Microprocessor Interface

JTAG

Auto

Divider

FRSYNC_8K_1PPS

MFRSYNC_2K_1PPS

APLL

Auto

Divider

OSCI

Output

Figure 1. Functional Block Diagram

REVISION 9 01/05/16

SYNCHRONIZATION MANAGEMENT WAN PLL AND

CLOCK GENERATIION FOR IEEE-1588

1 234 5

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