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82V3285PF PDF预览

82V3285PF

更新时间: 2024-02-05 04:27:16
品牌 Logo 应用领域
艾迪悌 - IDT 电信电信集成电路
页数 文件大小 规格书
147页 1386K
描述
Telecom Circuit, 1-Func, PQFP100, TQFP-100

82V3285PF 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:QFP
包装说明:LFQFP, QFP100,.63SQ,20针数:100
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.08JESD-30 代码:S-PQFP-G100
JESD-609代码:e0长度:14 mm
湿度敏感等级:3功能数量:1
端子数量:100最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP100,.63SQ,20
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):240电源:3.3 V
认证状态:Not Qualified座面最大高度:1.6 mm
子类别:Other Telecom ICs最大压摆率:0.528 mA
标称供电电压:3.3 V表面贴装:YES
电信集成电路类型:TELECOM CIRCUIT温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:20宽度:14 mm
Base Number Matches:1

82V3285PF 数据手册

 浏览型号82V3285PF的Datasheet PDF文件第1页浏览型号82V3285PF的Datasheet PDF文件第2页浏览型号82V3285PF的Datasheet PDF文件第4页浏览型号82V3285PF的Datasheet PDF文件第5页浏览型号82V3285PF的Datasheet PDF文件第6页浏览型号82V3285PF的Datasheet PDF文件第7页 
Table of Contents  
FEATURES.............................................................................................................................................................................. 9  
HIGHLIGHTS.................................................................................................................................................................................................... 9  
MAIN FEATURES ............................................................................................................................................................................................ 9  
OTHER FEATURES......................................................................................................................................................................................... 9  
APPLICATIONS....................................................................................................................................................................... 9  
DESCRIPTION....................................................................................................................................................................... 10  
FUNCTIONAL BLOCK DIAGRAM........................................................................................................................................ 11  
1 PIN ASSIGNMENT ........................................................................................................................................................... 12  
2 PIN DESCRIPTION .......................................................................................................................................................... 13  
3 FUNCTIONAL DESCRIPTION ......................................................................................................................................... 18  
3.1 RESET ........................................................................................................................................................................................................... 18  
3.2 MASTER CLOCK .......................................................................................................................................................................................... 18  
3.3 INPUT CLOCKS & FRAME SYNC SIGNAL ................................................................................................................................................. 19  
3.3.1 Input Clocks .................................................................................................................................................................................... 19  
3.3.2 Frame SYNC Input Signals ............................................................................................................................................................ 19  
3.4 INPUT CLOCK PRE-DIVIDER ...................................................................................................................................................................... 20  
3.5 INPUT CLOCK QUALITY MONITORING ..................................................................................................................................................... 21  
3.5.1 Activity Monitoring ......................................................................................................................................................................... 21  
3.5.2 Frequency Monitoring ................................................................................................................................................................... 22  
3.6 T0 / T4 DPLL INPUT CLOCK SELECTION .................................................................................................................................................. 23  
3.6.1 External Fast Selection (T0 only) .................................................................................................................................................. 23  
3.6.2 Forced Selection ............................................................................................................................................................................ 24  
3.6.3 Automatic Selection ....................................................................................................................................................................... 24  
3.7 SELECTED INPUT CLOCK MONITORING .................................................................................................................................................. 25  
3.7.1 T0 / T4 DPLL Locking Detection ................................................................................................................................................... 25  
3.7.1.1 Fast Loss .......................................................................................................................................................................... 25  
3.7.1.2 Coarse Phase Loss .......................................................................................................................................................... 25  
3.7.1.3 Fine Phase Loss ............................................................................................................................................................... 25  
3.7.1.4 Hard Limit Exceeding ....................................................................................................................................................... 25  
3.7.2 Locking Status ............................................................................................................................................................................... 25  
3.7.3 Phase Lock Alarm (T0 only) .......................................................................................................................................................... 26  
3.8 SELECTED INPUT CLOCK SWITCH ........................................................................................................................................................... 27  
3.8.1 Input Clock Validity ........................................................................................................................................................................ 27  
3.8.2 Selected Input Clock Switch ......................................................................................................................................................... 27  
3.8.2.1 Revertive Switch ............................................................................................................................................................... 27  
3.8.2.2 Non-Revertive Switch (T0 only) ........................................................................................................................................ 28  
3.8.3 Selected / Qualified Input Clocks Indication ................................................................................................................................ 28  
3.9 SELECTED INPUT CLOCK STATUS VS. DPLL OPERATING MODE ....................................................................................................... 29  
3.9.1 T0 Selected Input Clock vs. DPLL Operating Mode .................................................................................................................... 29  
3.9.2 T4 Selected Input Clock vs. DPLL Operating Mode .................................................................................................................... 31  
3.10 T0 / T4 DPLL OPERATING MODE ............................................................................................................................................................... 32  
3.10.1 T0 DPLL Operating Mode .............................................................................................................................................................. 32  
3.10.1.1 Free-Run Mode ................................................................................................................................................................ 32  
3.10.1.2 Pre-Locked Mode ............................................................................................................................................................. 32  
3.10.1.3 Locked Mode .................................................................................................................................................................... 32  
3.10.1.3.1 Temp-Holdover Mode .................................................................................................................................... 32  
Table of Contents  
3
December 9, 2008  

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