PRELIMINARY
FEMTOCLOCK™ JITTER ATTENUATOR &
FREQUENCY TRANSLATOR W/LVPECL OUTPUTS
ICS813253
GENERAL DESCRIPTION
FEATURES
• Three differential LVPECL outputs
The ICS813253 is a member of the HiperClockS™
ICS
family of high performance clock solutions from
IDT. The ICS813253 is a PLL based synchronous
clock generator that is optimized for Gigabit
Ethernet and PCI-Express clock jitter attenuation
• One differential input supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
HiPerClockS™
• Accepts input frequencies from 19.6MHz to 136MHz, includ-
ing: 25MHz, 62.5MHz, 100MHz and 125MHz input clocks
and frequency translation. The device contains two internal
frequency multiplication stages that are cascaded in series.The
first stage is a VCXO PLL that is optimized to provide
reference clock jitter attenuation. The second stage is a
FemtoClock frequency multiplier that provides the low
jitter, high frequency Gigabit Ethernet or PCI-Express
output clock.
• Attenuates the phase jitter of the input clock by using a low-
cost pullable funamental mode VCXO crystal
• Outputs common Gigabit Ethernet or PCI-Express clock rates
• VCXO PLL bandwidth can be optimized for jitter attenuation
and reference tracking using external loop filter connection
• Absolute pull range: 110ppm
• FemtoClock frequency multiplier provides low jitter,
Predivider and output divider multiplication ratios are selected
using device selection control pins. The multiplication ratios are
optimized to support most common clock rates used in Gigabit
Ethernet and PCI-Express applications. The VCXO requires
the use of an external, inexpensive pullable crystal. The VCXO
uses external passive loop filter components which allows
configuration of the PLL loop bandwidth and damping
characteristics.
high frequency output
• FemtoClock range: 490MHz - 680MHz
• RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.37ps (typical)
• Full 3.3Vsupply, or 3.3V Core/2.5V output supply
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
OE
LF
VCCA
VCC
VCCO
nQ0
Q0
PSEL0
VEE
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
PIN ASSIGNMENT
VCCO
nQ2
Q2
nQ1
Q1
ICS813253
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
FSEL0
VEE
G Package
Top View
PSEL1
9
16
15
14
13
FSEL1
nBypass
CLK
XTAL_OUT
XTAL_IN
VEE
10
11
12
nCLK
BLOCK DIAGRAM
External
Loop Filter Input
Q0
Pullup
nBypass
nQ0
Q1
0
Output
Divider
2, 4, 5, 25
Pulldown
CLK
FemtoClock
Frequency
Multiplier x25
Pre-Divider
1, 2.5,
Phase
Detector
VCXO
1
Pullup/Pulldown
nCLK
4, 5
nQ1
Q2
Pullup
PSEL0
Pullup
Pullup
VCXO Jitter Attenuation PLL
PSEL1
FSEL0
nQ2
Pullup
Pullup
FSEL1
OE
IDT™ / ICS™ JITTER ATTENUATOR/FREQUENCY TRANSLATOR
1
ICS813253AG REV. A JANUARY 5, 2007