8103609SA

更新时间： 2024-02-17 06:00:06

品牌	Logo	应用领域
德州仪器 - TI		可编程逻辑输入元件时钟
页数	文件大小	规格书
18页	355K
描述
STANDARD HIGH-SPEED PAL CIRCUITS

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数据手册

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8103609SA 数据手册

PAL16L8AM, PAL16L8A-2M, PAL16R4AM, PAL16R4A-2M

PAL16R6AM, PAL16R6A-2M, PAL16R8AM, PAL16R8A-2M

STANDARD HIGH-SPEED PAL CIRCUITS

SRPS016 – D2705, FEBRUARY 1984 – REVISED MARCH 1992

PARAMETER MEASUREMENT INFORMATION

5 V

From Output

Under Test

Test

Point

(see Note A)

LOAD CIRCUIT FOR

3-STATE OUTPUTS

3 V

Timing

Input

High-Level

1.5 V

1.5 V 1.5 V

Pulse

3 V

Data

Input

3 V

1.5 V

Low-Level

Pulse

1.5 V 1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PULSE DURATIONS

3 V

Output

Control

(low-level

enabling)

1.5 V

Input

1.5 V

dis

In-Phase

Output

1.5 V

≈ 3.3 V

Waveform 1

S1 Closed

(see Note B)

1.5 V

+ 0.5 V

Out-of-Phase

Output

(see Note D)

dis

1.5 V

≈ 0 V

Waveform 2

S1 Open

(see Note B)

1.5 V

– 0.5 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

NOTES: A. C includes probe and jig capacitance and is 50 pF for t and t , 5 pF for t

pd en dis

B. Waveform1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2

is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses have the following characteristics: PRR ≤ 10 MHz, t and t ≤ 2 ns, duty cycle = 50%

D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.

E. Equivalent loads may be used for testing.

Figure 1. Load Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SRPS016

1...9 10 111213 14 15...18

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