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7P640ATA3300I25 PDF预览

7P640ATA3300I25

更新时间： 2024-01-21 13:01:34
品牌 Logo 应用领域
美高森美 - MICROSEMI 内存集成电路
页数 文件大小 规格书
21页 103K
描述
Flash Card, 320MX16, 250ns, CARD-68

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中文翻译

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7P640ATA3300I25 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：CARD-68Reach Compliance Code：unknown
风险等级：5.85最长访问时间：250 ns
其他特性：CAN ALSO OPERATE WITH 5V SUPPLYJESD-30 代码：R-XXMA-X68
内存密度：5368709120 bit内存集成电路类型：FLASH CARD
内存宽度：16功能数量：1
端子数量：68字数：335544320 words
字数代码：320000000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：320MX16封装主体材料：UNSPECIFIED
封装形状：RECTANGULAR封装形式：MICROELECTRONIC ASSEMBLY
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
编程电压：3 V认证状态：Not Qualified
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：NO
技术：CMOS温度等级：INDUSTRIAL
端子形式：UNSPECIFIED端子位置：UNSPECIFIED
处于峰值回流温度下的最长时间：NOT SPECIFIED类型：NAND TYPE
Base Number Matches：1

7P640ATA3300I25 数据手册

 浏览型号7P640ATA3300I25的Datasheet PDF文件第5页浏览型号7P640ATA3300I25的Datasheet PDF文件第6页浏览型号7P640ATA3300I25的Datasheet PDF文件第7页浏览型号7P640ATA3300I25的Datasheet PDF文件第9页浏览型号7P640ATA3300I25的Datasheet PDF文件第10页浏览型号7P640ATA3300I25的Datasheet PDF文件第11页 
ATA PCMCIA Card  
ATA33 Series  
Card Signal Description  
Symbol  
WAIT#  
Type  
OUTPUT  
Name and Function  
WAIT: This signal outputs low level for purpose of delaying memory  
or I/O access cycle. In True IDE Mode this signal can be used as  
IORDY.  
BVD2  
SPKR#  
DASP#  
Input/Output  
Input/Output  
Battery Voltage Detect 2, Data audio output, Disk active/slave  
present: In memory card mode, BVD2 is always high. In I/O mode,  
SPKR# is held high: no digital audio signals. In True IDE Mode  
DASP# is Disk Active/Slave Present signal in Master/Slave  
handshake protocol.  
Battery Voltage Detect 1, Status Change, Pass Diagnostic: In  
memory card mode BVD1 Is set to high level. In I/O mode  
STSCHNG# is used to alert the host to changes in Status registers. In  
True IDE mode PDIG is the Pass Diagnostic signal in Master/Slave  
handshake protocol.  
BVD1  
STSCHNG#  
PDIAG#  
VS1, VS2  
CSEL#  
OUTPUT  
Input  
VOLTAGE SENSE: Notifies the host socket of the card's VCC  
requirements. VS1 and VS2 are open to indicate a 5V, 16 bit card has  
been inserted.  
Card Select: This signal is not used in memory and I/O mode. With  
internal pull up resistor this signal is used to configure this card as  
Master or Slave when configured in True IDE Mode. When this pin is  
GND, selected Master config, when pin is open the card is configured  
as a Slave.  
INPACK#  
Output  
Input Acknowledge: This signal is not used in memory mode. It is  
asserted by the card when the card is selected and responding to an  
I/O read cycle at the address that is on the address bus. This signal is  
used for the input data buffer control. In True IDE Mode this signal is  
not used and should not be connected at the host.  
IORD#  
IOWR#  
Input  
Input  
I/O Read: is used for control of read data in Task File area. This card  
respond to this signal only in I/O interface mode  
I/O Write: is used for control of data write in Task File area. This card  
respond to this signal only in I/O interface mode  
October 2001  
8
ATA30 Series  
PC Card Products  
1...567891011...21

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