PCMCIA Flash Memory Card
FLV Series
White Electronic Designs
CARD SIGNAL DESCRIPTION
Name and Function
Symbol
Type
A0 - A25
INPUT
ADDRESS INPUTS: A0 through A25 enable direct addressing of up to 64MB of memory on the card. Signal A0 is not
used in word access mode. A25 is the most significant bit
DQ0 - DQ15 INPUT/OUTPUT
DATA INPUT/OUTPUT: DQ0 THROUGH DQ15 constitute the bi-directional databus. DQ15 is the MSB.
CE1#, CE2#
INPUT
CARD ENABLE 1 AND 2: CE1# enables even byte accesses, CE2# enables odd byte accesses. Multiplexing A0, CE1#
and CE2# allows 8-bit hosts to access all data on DQ0 - DQ7.
OE#
WE#
INPUT
INPUT
OUTPUT ENABLE: Active low signal gating read data from the memory card.
WRITE ENABLE: Active low signal gating write data to the memory card.
RDY/BSY#(*)
OUTPUT
READY/BUSY OUTPUT: Indicates status of internally timed erase or program algorithms. A high output indicates that
the card is ready to accept accesses. A low output indicates that one or more devices in the memory card are busy with
internally timed erase or write activities.
CD1#, CD2#
WP
OUTPUT
OUTPUT
CARD DETECT 1 and 2: Provide card insertion detection. These signals are internally connected to ground on the card.
The host shall monitor these signals to detect card insertion (pulled-up on host side).
WRITE PROTECT: Write protect reflects the status of the Write Protect switch on the memory card. WP set to high
= write protected, providing internal hardware write lockout to the Flash array. If card does not include optional write
protect switch, this signal will be pulled low internally indicating write protect = “off”.
VPP1, VPP2
VCC
N.C.
PROGRAM/ERASE POWER SUPPLY: Provides programming voltages for card. Not connected for 3.3V/5V only card.
CARD POWER SUPPLY: 5.0V for all internal circuitry
GND
CARD GROUND
REG#
INPUT
INPUT
ATTRIBUTE MEMORY SELECT : Active low signal, enables access to attribute memory space,occupied by the Card
Information Structure (CIS) and Card Registers.
RST
RESET: Active high signal for placing card in Power-on default state. Reset can be used as a Power-Down control for
the memory array.
WAIT#
BVD1, BVD2
VS1, VS2
OUTPUT
OUTPUT
OUTPUT
WAIT#: This signal is pulled high internally for compatibility. No WAIT# states are generated.
BATTERY VOLTAGE DETECT: These signals are pulled high to maintain SRAM card compatibility.
VOLTAGE SENSE: Notifies the host socket of the card’s VCC requirements. VS1 and VS2 are open to indicate a 5V card
RFU
NC
RESERVED FOR FUTURE USE
NO INTERNAL CONNECTION TO CARD: pin may be driven or left floating
(*) Signals not supported by FLV51-FLV58 (NC)
FUNCTIONAL TRUTH TABLE
READ function
Common Memory
Attribute Memory
D15-D8
Function Mode
CE2#
H
CE1#
H
A0
X
L
OE#
X
WE#
X
REG#
X
D15-D8
D7-D0
REG#
D7-D0
High-Z
Standby Mode
High-Z
High-Z
X
L
L
L
L
High-Z
Byte Access (8 bits)
H
L
L
H
H
High-Z
Even-Byte
Odd-Byte
Even-Byte
High-Z
High-Z
Even-Byte
Not Valid
Even-Byte
High-Z
H
L
H
X
X
L
H
H
High-Z
High-Z
Word Access (16 bits)
Odd-Byte Only Access
L
L
L
H
H
Odd-Byte
Odd-Byte
Not Valid
Not Valid
L
H
L
H
H
WRITE function
Standby Mode
H
H
H
L
H
L
X
L
X
H
H
H
H
X
L
L
L
L
X
H
H
H
H
X
X
X
L
L
L
L
X
X
X
X
X
X
Byte Access (8 bits)
X
Even-Byte
Odd-Byte
Even-Byte
X
Even-Byte
L
H
X
X
X
X
Even-Byte
X
Word Access (16 bits)
Odd-Byte Only Access
L
Odd-Byte
Odd-Byte
L
H
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
June, 2003
Rev. 5
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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