Philips Semiconductors
Product specification
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger (3-State)
74LVC374A
Inputs can be driven from either 3.3V or 5V devices. In 3-State
operation, outputs can handle 5V. This feature allows the use of
these devices as translators in a mixed 3.3V/5V environment.
FEATURES
• 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic
• Supply voltage range of 2.7V to 3.6V
• Complies with JEDEC standard no. 8-1A
• CMOS low power consumption
The 74LVC374A is an octal D-type flip-flop featuring separate
D-type inputs for each flip-flop and 3-State outputs for bus-oriented
applications. A clock (CP) and an output enable (OE) input are
common to all flip-flops.
• Direct interface with TTL levels
The eight flip-flops will store the state of their individual D-inputs
that meet the setup and hold times requirements on the
LOW-to-HIGH CP transition.
• High impedance when V = 0V
CC
• 8-bit positive edge-triggered register
When OE is LOW, the contents of the eight flip-flops is available at
the outputs. When OE is HIGH, the outputs go to the high
impedance OFF-state. Operation of the OE input does not affect the
state of the flip-flops.
• Independent register and 3-State buffer operation
DESCRIPTION
The 74LVC374A is a high-performance, low-power, low-voltage,
Si-gate CMOS device, superior to most advanced CMOS
compatible TTL families.
The ’374’ is functionally identical to the ’574’, but the ’574’ has a
different pin arrangement.
QUICK REFERENCE DATA
GND = 0V; T
=25°C; t = t v 2.5ns
amb
r
f
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
Propagation delay
CP to Q
C = 50pF
L
t
f
/t
ns
PHL PLH
V
CC
= 3.3V
4.8
150
5.0
n
maximum clock frequency
Input capacitance
MHz
pF
max
C
C
I
Power dissipation capacitance per
flip-flop
Notes 1 and 2
20
pF
PD
NOTE:
1. C is used to determine the dynamic power dissipation (P in mW):
PD
D
2
2
P
= C x V
x f + S (C x V
x f ) where:
D
PD
CC
i
L
CC o
f = input frequency in MHz; C = output load capacity in pF;
i
L
f = output frequency in MHz; V = supply voltage in V;
o
CC
2
S (C x V
x f ) = sum of outputs.
L
CC
o
2. The condition is V = GND to V
I
CC
ORDERING INFORMATION
TEMPERATURE
RANGE
OUTSIDE
NORTH AMERICA
PACKAGES
NORTH AMERICA
PKG. DWG. #
20-Pin Plastic Shrink Small Outline (SO)
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
74LVC374A D
74LVC374A DB
74LVC374A PW
74LVC374A D
74LVC374A DB
7LVC374APW DH
SOT163-1
SOT339-1
SOT360-1
20-Pin Plastic Shrink Small Outline (SSOP) Type II
20-Pin Plastic Thin Shrink Small Outline (TSSOP) Type I
2
1998 Jul 29
853-1861 19802