Datasheet > 电信电路 > ATM/SONET/SDH 集成电路> 78P2352-IGTR/F

78P2352-IGTR/F

更新时间： 2024-01-09 08:15:14

品牌	Logo	应用领域
TERIDIAN		/
页数	文件大小	规格书
42页	754K
描述
Transceiver, 2-Func, PQFP128, LEAD FREE, LQFP-128

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技术参数
数据手册

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78P2352-IGTR/F 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Not Recommended	零件包装代码：	QFP
包装说明：	LFQFP, QFP128,.64SQ,16	针数：	128
Reach Compliance Code：	compliant	ECCN代码：	5A991
HTS代码：	8542.39.00.01	风险等级：	5.23
应用程序：	SONET;SDH	JESD-30 代码：	S-PQFP-G128
长度：	14 mm	湿度敏感等级：	3
功能数量：	1	端子数量：	128
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFQFP
封装等效代码：	QFP128,.64SQ,16	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE, FINE PITCH	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	3.3 V	认证状态：	Not Qualified
座面最大高度：	1.6 mm	子类别：	Digital Transmission Interfaces
最大压摆率：	0.35 mA	标称供电电压：	3.3 V
表面贴装：	YES	电信集成电路类型：	ATM/SONET/SDH TRANSCEIVER
温度等级：	INDUSTRIAL	端子形式：	GULL WING
端子节距：	0.4 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	14 mm
Base Number Matches：	1

78P2352-IGTR/F 数据手册

78P2352

Dual Channel

OC-3/ STM1-E/ E4 LIU

Receive Loss of Signal

Each of the serial NRZ transmit timing modes can be

configured in HW mode or SW mode as shown in

the table below.

The 78P2352 includes a Loss of Signal (LOS)

detector. When the peak value of the received CMI

signal is less than approximately 19dB below

nominal for approximately 110 UI, Receive Loss of

Signal is asserted. The Rx LOS signal is cleared

when the received signal is greater than

approximately 18dB below nominal for 110 UI.

HW Control Pins SW Control Bits

Serial Mode

SDI_PAR CKMODE PAR SMOD[1:0]

Synchronous

Low

n/a

Low

Floating

High

0 0

1 0

0 1

clock + data

Synchronous

data only

Plesiochronou

s data only

In ECL mode, the LOSx signal will be asserted when

there are no transitions for longer than 2.3µs. The

signal is cleared when there are more than 4

transitions in 32 UI. It is generally recommended to

use the LOS status signal from the optical

transceiver module.

Loop-timing

n/a

Synchronous (Re-timing) Tx Serial Modes

During Rx LOS conditions, the receive clock will

remain on the last selected phase tap of the Rx DLL

outputting a stable clock while the receive data

outputs are squelched and held at logic ‘0’.

In Figure 1, serial NRZ transmit data is input to

SIDxP/N pins at LVPECL levels. By default, the data

is latched in on the rising edge of SICKxP. An

integrated FIFO decouples the on chip and off chip

clocks and re-clocks the data using a clean

synthesized clock generated from the provided

reference clock. As such, the SICKxP/N clock

provided by the framer/mapper IC for both

channels must be source synchronous with the

provided reference clock when the FIFO is used.

Note: Rx Loss of Signal detection is disabled

during Local Loopback and Receive Monitor

Modes.

Receive Loss of Lock

The 78P2352 includes an optional Receiver Loss of

Lock detector that will flag if the recovered Rx clock

frequency differs from the reference clock by more

than ±100ppm in an interval greater than 420µs.

This condition is cleared when the frequencies are

less than ±100ppm off for more than 500µs.

System Reference Clock

CKREFP/N

NRZ

CMI

Coax

SIxDP/N

CMIxP/N

RXxP/N

XFMR

140 / 155 MHz

SIxCKP/N

Framer/

Mapper

TDK

Notes:

NRZ

78P2352

SOxCKP/N

SOxDP/N

1. During Rx Loss of Signal (RLOS), the Rx

Loss of Lock indicator is undefined and may

report either status.

140 / 155 MHz

Figure 1: Synchronous clock and data available

(Tx CDR bypassed, FIFO enabled)

2. For reliable operation, the LOLOR bit in the

Signal Control register should be toggled

upon power-up and configuration.

If an off-chip serial transmit clock is not available, as

in Figure 2, the 78P2352 can recover a Tx clock

from the serial NRZ data input and pass the data

through the clock decoupling FIFO. The data is then

re-clocked or re-timed using a clean synthesized

clock generated from the provided reference clock.

In this mode, the NRZ transmit source data for both

channels must be source synchronous with the

reference clock applied at CKREFP/N.

TRANSMITTER OPERATION

At the media interface, the transmit driver generates

an analog signal for transmission through either a

transformer and 75Ω coaxial cable or directly to a

fiber optics transceiver for electrical to optical

conversion.

System Reference Clock

At the host interface, the 78P2352 provides a

number interface options for compatibility with most

CKREFP/N

NRZ

CMI

Coax

off-the-shelf framers and custom ASICs.

CMIxP/N

SIxDP/N

XFMR

selectable 4-bit parallel or nibble interface is

available with both slave or master timing options as

well a serial LVPECL interface with various timing

recovery modes.

Framer/

Mapper

TDK

NRZ

_SOxCKP/N78P2352

140 / 155 MHz

SOxDP/N

RXxP/N

Figure 2: Synchronous data only

(Tx CDR enabled, FIFO enabled)

Page: 5 of 42

2006 Teridian Semiconductor Corporation

Rev. 2.4

1 2 3 456 7 8...42

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