78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit
RECEIVER OPERATION
FUNCTIONAL DESCRIPTION
The receiver accepts serial data, at 155.52Mbit/s or
139.264Mbit/s from the RXxP/N inputs. In CMI
mode, the CMI-coded inputs come from a coaxial
cable that is transformer-coupled to the chip. In NRZ
(optical) mode, the input pins receive NRZ LVPECL
level signals from an O/E converter.
The CMI signal first enters an AGC and a high
performance adaptive equalizer designed to
overcome inter-symbol interference caused by long
cable lengths. The variable gain differential amplifier
automatically controls the gain to maintain a
constant voltage level output regardless of the input
voltage level. In ECL (NRZ) mode, the input signals
bypass the adaptive equalizer.
The outputs of the data comparators are connected
to the clock recovery circuits. The clock recovery
system employs a digital PLL, which uses a
reference frequency derived from the clock applied
to the CKREFP/N pins.
In serial mode, the clock and data are transmitted
through the LVPECL drivers. In parallel mode, the
data is converted into four bit parallel segments
before being transmitted through the CMOS drivers.
The 78P2352 contains all the necessary transmit
and receive circuitry for connection between
139.264Mbit/s and 155.52Mbit/s line interfaces and
the digital universe. The chip is controllable through
pins or serial port register settings.
In hardware mode (pin control) the SPSL pin
must be low.
In software mode (SPSL pin high), control pins
are disabled and the 78P2352 must be
configured via the 4-wire serial port.
MODE SELECTION
The SDO_E4 pin or E4 register bit determines which
rate the device operates in according to the table
below. This control combined with CKSL also
selects the global reference frequency.
Rate
SDO_E4 pin
E4 bit
1
0
E4
High
STM-1, STS-3, OC-3 Low
The SEN_CMI pin or CMI register bit selects one of
two media for reception and transmission: coaxial
cable in CMI mode or optical fiber in ECL (NRZ)
mode. Independent channel operation is available
with register controls.
Receiver Monitor Mode
In CMI mode, the SCK_MON pin or MONx register
bit puts the receiver in monitor mode and adds
approximately 20dB of flat gain to the receive signal
before equalization. Rx Monitor Mode can handle
20dB of flat loss typical of monitoring points with up
to 6dB of cable loss. Note that Loss of Signal
detection is disabled during Rx Monitor Mode.
Media (coding)
75 ohm Coax (CMI)
Fiber (NRZ)
SEN_CMI pin
High
Low
CMI bit
1
0
The SDI_PAR pin or PAR register bit selects the
interface to the framer to be four-bit parallel CMOS
or serial LVPECL. For each interface there are
different transmit timing modes See TRANSMITTER
OPERATION section for more info.
Loss of Signal
The 78P2352 includes
a
ITU-T G.775/G.783
compliant Loss of Signal (LOS) detector. When the
received CMI signal is less than approximately 18dB
below nominal for 80 UI, the LOS pin is asserted.
The LOS signal is cleared when the received signal
is greater than approximately 17dB below nominal
for 80 UI. During LOS conditions, the receive data
outputs are squelched and held at logic ‘0’.
REFERENCE CLOCK
The 78P2352 requires a reference clock supplied to
the CKREFP/N pins. For reference frequencies of
77.76MHz or lower, the device accepts a single
ended CMOS input at CKREFP. For reference
frequencies of 139.264/155.52MHz, the device
accepts a differential LVPECL clock input at
CKREFP/N. The frequency of this reference input is
controlled by the rate selection and the CKSL control
pin or register bit.
Note: Loss of Signal detection is disabled during
Local Loopback and Receive Monitor Modes.
In ECL mode, the LOSx signal will be asserted when
there are no transitions for longer than 2.3µs. The
signal is cleared when there are more than 4
transitions in 32 UI.
Reference Frequency
CKSL pin
SDO_E4 low
SDO_E4 high
Low
19.44MHz
77.76MHz
155.52MHz
E4 bit = 0
19.44MHz
77.76MHz
155.52MHz
17.408MHz
Loss of Lock
Float
N/A
The 78P2352 will declare a loss of lock condition
when the recovered clock frequency differs from the
reference clock by more than 100ppm in an interval
greater than 420µs. This condition is cleared when
the frequencies are less than 100ppm off for more
than 500µs.
High
139.264MHz
E4 bit = 1
17.408MHz
N/A
CKSL[1:0] bits
0 0
1 0
1 1
139.264MHz
4
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