Datasheet > 电信电路 > ATM/SONET/SDH 集成电路> 78P2351-IGT

78P2351-IGT

更新时间： 2024-01-29 10:58:44

品牌	Logo	应用领域
TERIDIAN		ATM集成电路 SONET集成电路 SDH集成电路电信集成电路电信电路异步传输模式
页数	文件大小	规格书
42页	736K
描述
Single Channel OC-3/ STM1-E/ E4 LIU

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技术参数
数据手册

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78P2351-IGT 技术参数

是否Rohs认证：	符合	生命周期：	Not Recommended
包装说明：	QCCN, LCC56,.27SQ,16	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	Factory Lead Time：	7 weeks
风险等级：	5.58	模拟集成电路 - 其他类型：	ANALOG CIRCUIT
JESD-30 代码：	S-PQCC-N56	端子数量：	56
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCN
封装等效代码：	LCC56,.27SQ,16	封装形状：	SQUARE
封装形式：	CHIP CARRIER	电源：	3.3 V
认证状态：	Not Qualified	子类别：	Other Analog ICs
最大供电电流 (Isup)：	180 mA	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子形式：	NO LEAD	端子节距：	0.4 mm
端子位置：	QUAD	Base Number Matches：	1

78P2351-IGT 数据手册

78P2351

Single Channel

OC-3/ STM1-E/ E4 LIU

Reference

Clock

Plesiochronous Tx Serial Mode

Figure 3 represents a common condition where a

serial transmit clock is not available and/or the data

is not source synchronous to the reference clock

CKREFP/N

PI[3:0]D

CMI

Coax

4-bit CMOS TTL

34/39 MHz

CMIP/N

RXP/N

XFMR

PIxCK

provided to the 78P2351.

In this mode, the

Framer/

Mapper

TDK

78P2351 will recover a transmit clock from the serial

plesiochronous data and bypass the internal FIFO

and re-timing block. This mode is commonly used

for mezzanine cards, modules, and any application

where the reference clock can’t always be

synchronous to the transmit source clock/data.

78P2351

PO[3:0]D

POCK

4-bit CMOS TTL

34/39 MHz

Figure 4: Slave Parallel Mode

Reference

Clock

Reference

Clock

CKREFP

CKREFP/N

NRZ

CMI

Coax

PI[3:0]D

PTOCK

CMI

Coax

4-bit CMOS TTL

34/39 MHz

CMIP/N

RXP/N

SIDP/N

XFMR

CMIP/N

RXP/N

XFMR

Framer/

Mapper

TDK

NRZ

Framer/

Mapper

TDK

78P2351

SOCKP/N

SODP/N

140 / 155 MHz

78P2351

PO[3:0]D

POCK

4-bit CMOS TTL

34/39 MHz

Coax

XFMR

Figure 3: Plesiochronous data only

(Tx CDR enabled, FIFO bypassed)

Figure 5: Master Parallel Mode

Synchronous Parallel Modes

Transmit FIFO Description

In parallel modes, 4-bit CMOS data segments are

input to the chip with a 34.816MHz (E4 ÷ 4) or

38.88MHz (STM1 ÷ 4) synchronous clock. These

inputs are re-timed in a 4x8 clock decoupling FIFO

and then to a serializer for transmission. Because

the data is passed through the FIFO and re-timed

using a synthesized clock, the transmit nibble clock

and data must be source synchronous to the

provided reference clock.

Since the reference clock and transmit clock/data go

through different delay paths, it is inevitable that the

phase relationship between the two clocks can vary

in a bounded manner due to the fact that the

absolute delays in the two paths can vary over time.

The transmit FIFO allows long-term clock phase drift

between the Tx clock and system reference clock,

not exceeding +/- 25.6ns, to be handled without

transmit error. If the clock wander exceeds the

specified limits, the FIFO will over or under flow, and

the FERR register signal will be asserted. This

signal can be used to trigger an interrupt. This

interrupt event is automatically cleared when a FIFO

Reset (FRST) pulse is applied, and the FIFO is re-

centered.

For maximum compatibility with legacy ASICs, the

78P2351 can operate in both slave and master clock

modes as shown in Figures 4 and 5 respectively.

Note: A loop-timing mode is also available to

allow external remote loopbacks (i.e. line

loopback in framer). In this mode, the FIFO is

still enabled, but the transmit data will be re-

timed using the recovered receive clock.

Notes:

1) External remote loopbacks (i.e. loopback

within framer) are not possible in

synchronous operation (FIFO enabled)

unless the data is re-justified to be

synchronous to the system reference clock

or the 78P2351 is configured for loop-timing

operation.

2) During IC power-up or transmit power-up,

the clocks going to the FIFO may not be

stable and cause the FIFO to overflow or

underflow. As such, the FIFO should be

manually reset using FRST anytime the

transmitter is powered-up.

HW Control Pins SW Control Bits

SDI_PAR CKMODE

Parallel

Mode

PAR

PMODE

Slave

High

Low

Slave +

Float

*Loop-timing

Master

High

*To enable loop-timing in software mode, set

SMOD[1:0]=11

Page: 6 of 42

2006 Teridian Semiconductor Corporation

Rev. 2.4

1...3 4 567 8 9...42

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与78P2351-IGT相关器件

型号	品牌	描述	获取价格	数据表
78P2351-IGT/A04	TERIDIAN	Telecom IC,	获取价格
78P2351-IGT/A04	TDK	Digital Transmission Interface, CMOS, PQFP100	获取价格
78P2351-IGT/A04/F	TERIDIAN	Telecom IC,	获取价格
78P2351-IGT/A04R	TDK	Digital Transmission Interface, CMOS, PQFP100	获取价格
78P2351-IGT/A04R/F	TDK	Digital Transmission Interface, CMOS, PQFP100	获取价格
78P2351-IGT/A04R/F	TERIDIAN	Telecom IC,	获取价格

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