Datasheet > 78P2344JAT-IGT/F

78P2344JAT-IGT/F

更新时间： 2024-02-11 17:20:13

品牌	Logo	应用领域
东电化 - TDK		PC 电信电信集成电路
页数	文件大小	规格书
36页	388K
描述
PCM Transceiver, 1-Func, PQFP100, LEAD FREE, TQFP-100

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78P2344JAT-IGT/F 技术参数

生命周期：	Obsolete	包装说明：	LEAD FREE, TQFP-100
Reach Compliance Code：	unknown	风险等级：	5.57
JESD-30 代码：	S-PQFP-G100	长度：	14 mm
功能数量：	1	端子数量：	100
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFQFP
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE, FINE PITCH
认证状态：	Not Qualified	座面最大高度：	1.6 mm
标称供电电压：	3.3 V	表面贴装：	YES
电信集成电路类型：	PCM TRANSCEIVER	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	宽度：	14 mm
Base Number Matches：	1

78P2344JAT-IGT/F 数据手册

78P2344JAT

4-port E3/DS3/STS-1 LIU

with Jitter Attenuator

Elastic Store Depth

SERIAL CONTROL INTERFACE

To optimize the trade-off between data latency and

clock wander tolerance, the FIFO elastic store depth

can be selected through the serial port by writing to

the Jitter Attenuator Control Register (JACR) as

follows:

The serial port controlled register allows a generic

controller to interface with the 78P2344JAT. It is

used for mode settings, diagnostics and test, and

the retrieval of status and performance information.

The serial interface consists of four pins: Chip Select

(CS), Serial Clock (SCK), Serial Data In (SDI), and

Serial Data Out (SDO). The CS pin initiates the

read and write operations. It can also be used to

select a particular device allowing SCK, SDI and

SDO to be bussed together. SCK is the clock input

that times the data on SDI and SDO. Data on SDI is

latched in on the rising-edge of SCK, and data on

SDO is clocked out using the falling edge of SCK.

ESP[1:0]

Elastic Store Depth

bits

Pass-Through mode

16 UI

32 UI

64 UI (default)

SDI is used to insert mode, address, and register

data into the chip. Address and Data information

are input least significant bit (LSB) first.

The Elastic Store Depth selects the nominal FIFO

read pointer address. The total or maximum elastic

store depth is set to be twice as deep as the nominal

pointer address. The circular buffer length is always

twice as long as the nominal pointer address.

SDO is a tristate capable output. It is used to output

normally high impedance, and is enabled only

during the duration when register data is being

POWER-DOWN FUNCTION

clocked out.

Read data is clocked out least

Power-down control is provided to allow the

transceivers to be shut off individually. Transmit and

receive power-down can be set independently via

the PDTX and PDRX bits in the Mode Control

set PDTX for each channel. The Serial Control

Interface and Configuration Registers are not

affected by power-down.

significant bit (LSB) first.

If SDI coming out of the micro-controller chip is also

tristate capable, SDI and SDO can be connected

together to simplify connections.

The maximum clock frequency for register access is

20MHz.

INTERNAL POWER-ON RESET

The 78P2344JAT includes on-chip Power-On Reset

(POR) function to ensure the serial-port registers are

initialized to known default states upon power-up.

This reset signal also sets all state machines within

the transceivers to nominal operational states. The

internal reset signal is also brought out to the POR

pin. This pin is a multi-function pin which allows for

the following:

1) Override the internal POR signal by driving in an

external active-low reset signal;

2) Monitor the state of the internal POR signal (for

test and debug only);

3) Add external capacitor to delay the release of

the internal power-on reset signal to allow the

MSL0 pin to stabilize prior to release of reset

(approximately 8µs per nF added).

The internal resistance of the POR pin is

approximately 5kΩ.

- 6 -

1...3 4 567 8 9...36

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与78P2344JAT-IGT/F相关器件

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78P2344JAT-IGT/F/A07	TERIDIAN	PCM Transceiver, 1-Func, PQFP100, LEAD FREE, LQFP-100	获取价格
78P2344JAT-IGTR	TERIDIAN	暂无描述	获取价格
78P2344JAT-IGTR/F/A07	TERIDIAN	PCM Transceiver, 1-Func, PQFP100, LEAD FREE, LQFP-100	获取价格
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78P2351-IGT	TERIDIAN	Single Channel OC-3/ STM1-E/ E4 LIU	获取价格

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