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78P2342-IGT/F/A07 PDF预览

78P2342-IGT/F/A07

更新时间: 2024-02-06 08:27:18
品牌 Logo 应用领域
美信 - MAXIM PC电信电信集成电路
页数 文件大小 规格书
36页 340K
描述
PCM Transceiver, 1-Func, PQFP100, LEAD FREE, LQFP-100

78P2342-IGT/F/A07 技术参数

生命周期:Obsolete包装说明:LEAD FREE, LQFP-100
Reach Compliance Code:unknown风险等级:5.56
JESD-30 代码:S-PQFP-G100长度:14 mm
功能数量:1端子数量:100
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
认证状态:Not Qualified座面最大高度:1.6 mm
标称供电电压:3.3 V表面贴装:YES
电信集成电路类型:PCM TRANSCEIVER温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD宽度:14 mm
Base Number Matches:1

78P2342-IGT/F/A07 数据手册

 浏览型号78P2342-IGT/F/A07的Datasheet PDF文件第1页浏览型号78P2342-IGT/F/A07的Datasheet PDF文件第2页浏览型号78P2342-IGT/F/A07的Datasheet PDF文件第3页浏览型号78P2342-IGT/F/A07的Datasheet PDF文件第5页浏览型号78P2342-IGT/F/A07的Datasheet PDF文件第6页浏览型号78P2342-IGT/F/A07的Datasheet PDF文件第7页 
78P2342JAT  
2-port E3/DS3/STS-1 LIU  
with Jitter Attenuator  
On the transmit side, when the ENDEC is enabled,  
NRZ input data is encoded to Positive and Negative  
AMI logic data following the B3ZS (for DS3/STS-1)  
or HDB3 (for E3) substitution codes. The NRZ data  
is input to the TPOS pin as shown below:  
B3ZS/HDB3 ENDEC WITH LINE CODE VIOLATION  
DETECT  
The 78P2342JAT includes a selectable B3ZS/HDB3  
Encoder/Decoder (ENDEC). The ENDEC function  
can be enabled or disabled through pin selection or  
register setting as shown below.  
ENDECB  
TPOSx  
TNEGx  
bit/pin  
0 / L  
ENDECB  
RPOSx  
RNEGx  
NRZ data  
‘Don’t Care’  
bit/pin  
1 / H  
Positive AMI  
Negative AMI  
Receive Line Code  
Violation Indicator  
0 / L  
NRZ data  
TRANSMITTER OPERATION  
1 / H  
Positive AMI  
Negative AMI  
Both transmitters are enabled by their corresponding  
TXEN bit. When enabled, each transmitter accepts  
logic level clock and data signals and generates  
current pulses on the LOUTPx and LOUTNx pins.  
When properly connected to a 1:2CT center-tapped  
transformer, a standards compliant AMI pulse is  
When the ENDEC is enabled, the decoder  
generates a composite NRZ logic data stream  
following the B3ZS (for DS3/STS-1) or HDB3 (for E3)  
substitution codes via the RPOSx pins:  
generated which can drive a 75  
coaxial cable.  
The decoder also detects Receive Line Code  
Violations (RLCV) and outputs a pulse via the  
RNEG pin. Three different classes of line code  
violations are detected.  
When the recommended transformer is used and  
when DS3 mode is selected, the transmitted pulse  
shape at the end of the 75  
terminated cable of 0 to  
450 feet will fit the DS3 template in ANSI T1.102-  
1993 and Telcordia GR-499-CORE. For STS-1  
applications, the transmitted pulse for a short cable  
meets the requirements of Telcordia GR-253-CORE.  
For E3 applications, the transmitted pulse for a short  
cable meets the requirements of ITU-T G.703.  
1) Too many zeros:  
More than two (three)  
consecutive zeros in B3ZS (HDB3) mode.  
2) Not enough zeros between bipolar pulse (B)  
and bipolar violation pulse (V): (B,V) for B3ZS.  
(B,V) or (B,0,V) for HDB3.  
3) Code violation: Even number of bipolar pulses  
(B) detected between bipolar violation pulses  
(V).  
In either DS3 and STS-1 modes, the LBOx pin or  
LBO bit should be set high for short cable (< 225 ft),  
and should be set low for long cable (> 225 ft). The  
LBO settings are ignored in E3 mode.  
When the ENDEC is disabled, the 78P2342JAT  
outputs a dual rail data stream via the RPOSx and  
RNEGx pins. In this mode, the Framer/Mapper  
providing the ENDEC function typically detects Line  
Code Violations.  
RCLK/TCLK POLARITY REVERSAL  
To simplify the interface with various framer circuitry,  
TCLK polarity can be internally inverted by setting  
the TCLKP bit, and RCLK polarity can be inverted  
by setting the RCLKP bit. Both bits are located in  
the Master Control Register (MSCR).  
REMOTE (DIGITAL) LOOPBACK  
When the Register Control bit, REGEN, is disabled  
and the LPBKx pin is floating; or when the Register  
Control bit, REGEN, is enabled and the RLBK bit is  
set, RCLKx, RNEGx, and RPOSx outputs are  
internally looped back to the TCLKx, TNEGx, and  
TPOSx inputs respectively.  
Page 4 of 36  
2005 Teridian Semiconductor Corporation  
Rev 2.2  

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