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74HCT4353N

更新时间： 2024-01-21 09:51:23
品牌 Logo 应用领域
恩智浦 - NXP 复用器开关复用器或开关信号电路光电二极管
页数 文件大小 规格书
16页 139K
描述
Triple 2-channel analog multiplexer/demultiplexer with latch

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74HCT4353N 技术参数

生命周期：Obsolete包装说明：,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.83模拟集成电路 - 其他类型：SINGLE-ENDED MULTIPLEXER
JESD-30 代码：X-XUUC-N负电源电压最大值（Vsup）：-5 V
负电源电压最小值（Vsup）：-1 V标称负供电电压 (Vsup)：-4.5 V
信道数量：2功能数量：3
标称断态隔离度：50 dB通态电阻匹配规范：6 Ω
最大通态电阻 (Ron)：130 Ω最高工作温度：125 °C
最低工作温度：-40 °C封装主体材料：UNSPECIFIED
封装形状：UNSPECIFIED封装形式：UNCASED CHIP
认证状态：Not Qualified最大供电电压 (Vsup)：5 V
最小供电电压 (Vsup)：1 V标称供电电压 (Vsup)：4.5 V
表面贴装：YES最长断开时间：45 ns
最长接通时间：45 ns技术：CMOS
温度等级：AUTOMOTIVE端子形式：NO LEAD
端子位置：UPPERBase Number Matches：1

74HCT4353N 数据手册

 浏览型号74HCT4353N的Datasheet PDF文件第1页浏览型号74HCT4353N的Datasheet PDF文件第3页浏览型号74HCT4353N的Datasheet PDF文件第4页浏览型号74HCT4353N的Datasheet PDF文件第5页浏览型号74HCT4353N的Datasheet PDF文件第6页浏览型号74HCT4353N的Datasheet PDF文件第7页 
Philips Semiconductors  
Product specification  
Triple 2-channel analog  
multiplexer/demultiplexer with latch  
74HC/HCT4353  
multiplexer has two independent inputs/outputs (nY0 and  
nY1), a common input/output (nZ) and select inputs (S1 to  
S3).  
FEATURES  
• Wide analog input voltage range: ± 5 V  
• Low “ON” resistance:  
Each multiplexer/demultiplexer contains two bidirectional  
analog switches, each with one side connected to an  
independent input/output (nY0 and nY1) and the other side  
connected to a common input/output (nZ).  
80 Ω (typ.) at VCC − VEE = 4.5 V  
70 Ω (typ.) at VCC − VEE = 6.0 V  
60 Ω (typ.) at VCC − VEE = 9.0 V  
• Logic level translation:  
With E1 LOW and E2 HIGH, one of the two switches is  
selected (low impedance ON-state) by S1 to S3.  
The data at the select inputs may be latched by using the  
active LOW latch enable input (LE). When LE is HIGH, the  
latch is transparent. When either of the two enable inputs,  
E1 (active LOW) and E2 (active HIGH), is inactive, all  
analog switches are turned off.  
to enable 5 V logic to communicate with ± 5 V analog  
signals  
• Typical “break before make” built in  
• Address latches provided  
• Output capability: non-standard  
• ICC category: MSI  
V
CC and GND are the supply voltage pins for the digital  
control inputs (S1 to S3, LE, E1 and E2). The VCC to GND  
ranges are 2.0 to 10.0 V for HC and 4.5 to 5.5 V for HCT.  
The analog inputs/outputs (nY0 and nY1, and nZ) can  
swing between VCC as a positive limit and VEE as a  
negative limit. VCC − VEE may not exceed 10.0 V.  
GENERAL DESCRIPTION  
The 74HC/HCT4353 are high-speed Si-gate CMOS  
devices. They are specified in compliance with JEDEC  
standard no. 7A.  
The 74HC/HCT4353 are triple 2-channel analog  
multiplexers/demultiplexers with two common enable  
inputs (E1 and E2) and a latch enable input (LE). Each  
For operation as a digital multiplexer/demultiplexer, VEE is  
connected to GND (typically ground).  
QUICK REFERENCE DATA  
V
EE = GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns  
TYPICAL  
SYMBOL  
PARAMETER  
CONDITIONS  
UNIT  
ns  
HC  
HCT  
t
PZH/ tPZL  
turn “ON” time E1, E2 or Sn to Vos  
turn “OFF” time E1, E2 or Sn to Vos  
input capacitance  
CL = 50 pF; RL = 1 kΩ; 29  
VCC = 5 V  
21  
22  
tPHZ/ tPLZ  
CI  
20  
ns  
pF  
pF  
3.5  
3.5  
23  
CPD  
power dissipation capacitance per switch  
max. switch capacitance  
independent (Y)  
notes 1 and 2  
23  
CS  
5
8
5
8
pF  
pF  
common (Z)  
Notes  
∑ {(CL ×CS) × VCC2 × fo} = sum of outputs  
VCC = supply voltage in V  
1. CPD is used to determine the dynamic power  
dissipation (PD in µW):  
2. For HC the condition is VI = GND to VCC  
PD =  
C
For HCT the condition is VI = GND to VCC − 1.5 V  
PD × VCC2 × fi + ∑ {(CL + CS) × VCC2 × fo} where:  
fi = input frequency in MHz  
ORDERING INFORMATION  
CL = output load capacitance in pF  
fo = output frequency in MHz  
CS = max. switch capacitance in pF  
See “74HC/HCT/HCU/HCMOS Logic Package  
Information”.  
December 1990  
2
1234567...16

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