5秒后页面跳转
74HC4094PW-Q100 PDF预览

74HC4094PW-Q100

更新时间: 2024-02-13 17:02:01
品牌 Logo 应用领域
安世 - NEXPERIA /
页数 文件大小 规格书
19页 288K
描述
8-stage shift-and-store bus register

74HC4094PW-Q100 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:TSSOP包装说明:4.40 MM, PLASTIC, MO-153, SOT403-1, TSSOP-16
针数:16Reach Compliance Code:compliant
风险等级:7.96Base Number Matches:1

74HC4094PW-Q100 数据手册

 浏览型号74HC4094PW-Q100的Datasheet PDF文件第2页浏览型号74HC4094PW-Q100的Datasheet PDF文件第3页浏览型号74HC4094PW-Q100的Datasheet PDF文件第4页浏览型号74HC4094PW-Q100的Datasheet PDF文件第5页浏览型号74HC4094PW-Q100的Datasheet PDF文件第6页浏览型号74HC4094PW-Q100的Datasheet PDF文件第7页 
74HC4094-Q100;  
74HCT4094-Q100  
8-stage shift-and-store bus register  
Rev. 2 — 14 November 2018  
Product data sheet  
1. General description  
The 74HC4094-Q100; 74HCT4094-Q100 is an 8-bit serial-in/serial or parallel-out shift register with  
a storage register and 3-state outputs. Both the shift and storage register have separate clocks.  
The device features a serial input (D) and two serial outputs (QS1 and QS2) to enable cascading.  
Data is shifted on the LOW-to-HIGH transitions of the CP input. Data is available at QS1 on the  
LOW-to-HIGH transitions of the CP input to allow cascading when clock edges are fast. The same  
data is available at QS2 on the next HIGH-to-LOW transition of the CP input to allow cascading  
when clock edges are slow. The data in the shift register is transferred to the storage register  
when the STR input is HIGH. Data in the storage register appears at the outputs whenever the  
output enable input (OE) is HIGH. A LOW on OE causes the outputs to assume a high-impedance  
OFF-state. Operation of the OE input does not affect the state of the registers. Inputs include clamp  
diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of  
VCC  
.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100  
(Grade 1) and is suitable for use in automotive applications.  
2. Features and benefits  
Automotive product qualification in accordance with AEC-Q100 (Grade 1)  
Specified from -40 °C to +85 °C and from -40 °C to +125 °C  
Complies with JEDEC standard JESD7A  
Input levels:  
For 74HC4094-Q100: CMOS level  
For 74HCT4094-Q100: TTL level  
Low-power dissipation  
ESD protection:  
MIL-STD-883, method 3015 exceeds 2000 V  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V (C = 200 pF; R = 0 Ω)  
3. Applications  
Serial-to-parallel data conversion  
Remote control holding register  
 
 
 

与74HC4094PW-Q100相关器件

型号 品牌 描述 获取价格 数据表
74HC4094PW-T NXP IC HC/UH SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, 4

获取价格

74HC4094-Q100 NEXPERIA 8-stage shift-and-store bus register

获取价格

74HC42 NXP BCD to decimal decoder 1-of-10

获取价格

74HC423 NXP Dual retriggerable monostable multivibrator with reset

获取价格

74HC423BQ NXP Dual retriggerable monostable multivibrator with reset

获取价格

74HC423BQ NEXPERIA Dual retriggerable monostable multivibrator with resetProduction

获取价格