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74HC32-Q100 PDF预览

74HC32-Q100

更新时间: 2024-02-19 18:26:16
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安世 - NEXPERIA /
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13页 229K
描述
Quad 2-input OR gate

74HC32-Q100 数据手册

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Nexperia  
74HC32-Q100; 74HCT32-Q100  
Quad 2-input OR gate  
Symbol Parameter  
Conditions  
25 °C  
-40 °C to -40 °C to Unit  
+85 °C  
+125 °C  
Min Typ Max  
Max  
Max  
74HCT32-Q100  
tpd  
propagation delay nA, nB to nY; see Fig. 6  
VCC = 4.5 V  
[1]  
-
-
-
-
11  
9
24  
-
30  
-
36  
-
ns  
ns  
ns  
pF  
VCC = 5.0 V; CL = 15 pF  
tt  
transition time  
VCC = 4.5 V; see Fig. 6  
[2]  
[3]  
7
15  
-
19  
-
22  
-
CPD  
power dissipation per package; VI = GND to VCC - 1.5 V  
capacitance  
28  
[1] tpd is the same as tPHL and tPLH  
.
[2] tt is the same as tTHL and tTLH  
.
[3] CPD is used to determine the dynamic power dissipation (PD in μW):  
PD = CPD × VCC2 × fi × N + Σ (CL × VCC2 × fo) where:  
fi = input frequency in MHz;  
fo = output frequency in MHz;  
CL = output load capacitance in pF;  
VCC = supply voltage in V;  
N = number of inputs switching;  
Σ (CL × VCC2 × fo) = sum of outputs.  
10.1. Waveforms  
V
I
nA, nB input  
V
M
GND  
t
t
PLH  
PHL  
V
V
OH  
Y
V
M
nY output  
V
X
V
OL  
t
t
TLH  
THL  
aaa-004037  
Measurement points are given in Table 8.  
VOL and VOH are typical voltage output levels that occur with the output load.  
Fig. 6. Input to output propagation delays and output transition times  
Table 8. Measurement points  
Type  
Input  
VM  
Output  
VM  
VX  
VY  
74HC32-Q100  
74HCT32-Q100  
0.5VCC  
1.3 V  
0.5VCC  
1.3 V  
0.1VCC  
0.1VCC  
0.9VCC  
0.9VCC  
©
74HC_HCT32_Q100  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2019. All rights reserved  
Product data sheet  
Rev. 2 — 30 September 2019  
6 / 13  
 
 
 
 

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