74F533FMX

更新时间： 2024-09-23 04:28:47

品牌	Logo	应用领域
美国国家半导体 - NSC		锁存器
页数	文件大小	规格书
8页	168K
描述
Octal Transparent Latch with TRI-STATE Outputs

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中文翻译

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数据手册

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74F533FMX 数据手册

Unit Loading/Fan Out

54F/74F

Pin Names

Description

U.L.

Input I /I

IH IL

Output I /I

HIGH/LOW

OH OL

20 mA/ 0.6 mA

D –D

Data Inputs

1.0/1.0

Latch Enable Input (Active HIGH)

Output Enable Input (Active LOW)

Complementary TRI-STATE Outputs

1.0/1.0

20 mA/ 0.6 mA

O –O

150/40 (33.3)

3 mA/24 mA (20 mA)

Function Table

Inputs

Output

HIGH Voltage Level

LOW Voltage Level

Immaterial

Functional Description

The ’F533 contains eight D-type latches with TRI-STATE

output buffers. When the Latch Enable (LE) input is HIGH,

data on the D inputs enters the latches. In this condition

the latches are transparent, i.e., a latch output will change

state each time its D input changes. When LE is LOW, the

latches store the information that was present on the D in-

puts a setup time preceding the HIGH-to-LOW transition of

LE. The TRI-STATE buffers are controlled by the Output

Enable (OE) input. When OE is LOW, the buffers are in the

bi-state mode. When OE is HIGH the buffers are in the high

impedance mode but this does not interfere with entering

new data into the latches.

Logic Diagram

TL/F/9548–5

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

123 4 5 6 7 8

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