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74F193SC

更新时间： 2024-02-08 02:25:05
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 光电二极管
页数 文件大小 规格书
9页 776K
描述
F/FAST SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO16, 0.150 INCH, MS-012, SOIC-16

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74F193SC 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP,针数：16
Reach Compliance Code：unknown风险等级：5.68
Is Samacsys：N其他特性：TCO UP AND TCO DOWN OUTPUTS; SEPARATE UP/DOWN CLOCK
计数方向：BIDIRECTIONAL系列：F/FAST
JESD-30 代码：R-PDSO-G16JESD-609代码：e3
长度：9.9 mm负载/预设输入：YES
逻辑集成电路类型：BINARY COUNTER工作模式：SYNCHRONOUS
湿度敏感等级：1位数：4
功能数量：1端子数量：16
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260传播延迟（tpd）：13.5 ns
认证状态：COMMERCIAL座面最大高度：1.75 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：TTL温度等级：COMMERCIAL
端子面层：MATTE TIN端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：3.9 mm最小 fmax：90 MHz
Base Number Matches：1

74F193SC 数据手册

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Unit Loading/Fan Out  
Input IIH/IIL  
U.L.  
Pin Names  
Description  
Output IOH/IOL  
HIGH/LOW  
1.0/3.0  
CPU  
CPD  
MR  
Count Up Clock Input (Active Rising Edge)  
Count Down Clock Input (Active Rising Edge)  
Asynchronous Master Reset Input (Active HIGH)  
Asynchronous Parallel Load Input (Active LOW)  
Parallel Data Inputs  
20 µA/−1.8 mA  
20 µA/−1.8 mA  
20 µA/−0.6 mA  
20 µA/−0.6 mA  
20 µA/−0.6 mA  
−1 mA/20 mA  
−1 mA/20 mA  
−1 mA/20 mA  
1.0/3.0  
1.0/1.0  
PL  
1.0/1.0  
P0–P3  
Q0–Q3  
TCD  
TCU  
1.0/1.0  
Flip-Flop Outputs  
50/33.3  
50/33.3  
50/33.3  
Terminal Count Down (Borrow) Output (Active LOW)  
Terminal Count Up (Carry) Output (Active LOW)  
Functional Description  
Function Table  
The 74F193 is a 4-bit binary synchronous up/down (revers-  
ible) counter. It contains four edge-triggered flip-flops, with  
internal gating and steering logic to provide master reset,  
individual preset, count up and count down operations.  
CPU  
CPD  
MR  
H
L
PL  
X
Mode  
X
X
H
X
X
H
H
Reset (Asyn.)  
Preset (Asyn.)  
No Change  
Count Up  
L
A LOW-to-HIGH transition on the CP input to each flip-flop  
causes the output to change state. Synchronous switching,  
as opposed to ripple counting, is achieved by driving the  
steering gates of all stages from a common Count Up line  
and a common Count Down line, thereby causing all state  
changes to be initiated simultaneously. A LOW-to-HIGH  
transition on the Count Up input will advance the count by  
one; a similar transition on the Count Down input will  
decrease the count by one. While counting with one clock  
input, the other should be held HIGH, as indicated in the  
Function Table.  
L
H
H
H
L
L
H
Count Down  
H = HIGH Voltage Level  
L = LOW Voltage Level  
X = Immaterial  
= LOW-to-HIGH Clock Transition  
State Diagram  
The Terminal Count Up (TCU) and Terminal Count Down  
(TCD) outputs are normally HIGH. When the circuit has  
reached the maximum count state 15, the next HIGH-to-  
LOW transition of the Count Up Clock will cause TCU to go  
LOW. TCU will stay LOW until CPU goes HIGH again, thus  
effectively repeating the Count Up Clock, but delayed by  
two gate delays. Similarly, the TCD output will go LOW  
when the circuit is in the zero state and the Count Down  
Clock goes LOW. Since the TC outputs repeat the clock  
waveforms, they can be used as the clock input signals to  
the next higher order circuit in a multistage counter.  
TCU = Q0 • Q1 • Q2 • Q3 • CPU  
TCD = Q0• Q1 • Q2 • Q3 • CPD  
The 74F193 has an asynchronous parallel load capability  
permitting the counter to be preset. When the Parallel Load  
(PL) and the Master Reset (MR) inputs are LOW, informa-  
tion present on the Parallel Data input (P0–P3) is loaded  
into the counter and appears on the outputs regardless of  
the conditions of the clock inputs. A HIGH signal on the  
Master Reset input will disable the preset gates, override  
both clock inputs, and latch each Q output in the LOW  
state. If one of the clock inputs is LOW during and after a  
reset or load operation, the next LOW-to-HIGH transition of  
that clock will be interpreted as a legitimate signal and will  
be counted.  
www.fairchildsemi.com  
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