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74F163ASCX PDF预览

74F163ASCX

更新时间： 2024-02-26 22:29:34
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 计数器触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
8页 96K
描述
Synchronous Presettable Binary Counter

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74F163ASCX 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：DIP,针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.27其他特性：TCO OUTPUT
计数方向：UP系列：F/FAST
JESD-30 代码：R-PDIP-T16负载/预设输入：YES
逻辑集成电路类型：BINARY COUNTER工作模式：SYNCHRONOUS
位数：4功能数量：1
端子数量：16最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装形状：RECTANGULAR
封装形式：IN-LINE传播延迟（tpd）：11 ns
认证状态：Not Qualified最大供电电压 (Vsup)：5.25 V
最小供电电压 (Vsup)：4.75 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：TTL
温度等级：COMMERCIAL端子形式：THROUGH-HOLE
端子位置：DUAL触发器类型：POSITIVE EDGE
最小 fmax：120 MHzBase Number Matches：1

74F163ASCX 数据手册

 浏览型号74F163ASCX的Datasheet PDF文件第1页浏览型号74F163ASCX的Datasheet PDF文件第2页浏览型号74F163ASCX的Datasheet PDF文件第4页浏览型号74F163ASCX的Datasheet PDF文件第5页浏览型号74F163ASCX的Datasheet PDF文件第6页浏览型号74F163ASCX的Datasheet PDF文件第7页 
Functional Description  
The 74F161A and 74F163A count in modulo-16 binary  
sequence. From state 15 (HHHH) they increment to state 0  
(LLLL). The clock inputs of all flip-flops are driven in paral-  
lel through a clock buffer. Thus all changes of the Q outputs  
(except due to Master Reset of the 74F161A) occur as a  
result of, and synchronous with, the LOW-to-HIGH transi-  
tion of the CP input signal. The circuits have four funda-  
mental modes of operation, in order of precedence:  
asynchronous reset (74F161A), synchronous reset  
(74F163A), parallel load, count-up and hold. Five control  
inputs—Master Reset (MR, 74F161A), Synchronous Reset  
(SR, 74F163A), Parallel Enable (PE), Count Enable Paral-  
lel (CEP) and Count Enable Trickle (CET)—determine the  
mode of operation, as shown in the Mode Select Table. A  
LOW signal on MR overrides all other inputs and asynchro-  
nously forces all outputs LOW. A LOW signal on SR over-  
rides counting and parallel loading and allows all outputs to  
go LOW on the next rising edge of CP. A LOW signal on PE  
overrides counting and allows information on the Parallel  
Data (Pn) inputs to be loaded into the flip-flops on the next  
rising edge of CP. With PE and MR ('F161A) or SR  
(74F163A) HIGH, CEP and CET permit counting when  
both are HIGH. Conversely, a LOW signal on either CEP or  
CET inhibits counting.  
The 74F161A and 74F163A use D-type edge triggered flip-  
flops and changing the SR, PE, CEP and CET inputs when  
the CP is in either state does not cause errors, provided  
that the recommended setup and hold times, with respect  
to the rising edge of CP, are observed.  
The Terminal Count (TC) output is HIGH when CET is  
HIGH and the counter is in state 15. To implement synchro-  
nous multi-stage counters, the TC outputs can be used  
with the CEP and CET inputs in two different ways. Please  
refer to the 74F568 data sheet. The TC output is subject to  
decoding spikes due to internal race conditions and is  
therefore not recommended for use as a clock or asynchro-  
nous reset for flip-flops, counters or registers.  
Logic Equations: Count Enable = CEP • CET • PE  
TC = Q0 • Q1 • Q2 • Q3 • CET  
Mode Select Table  
State Diagram  
Action on the Rising  
Clock Edge (  
Reset (Clear)  
SR  
(Note 1)  
CE  
P
PE CET  
)
L
X
L
X
X
H
L
X
X
H
X
L
H
H
H
H
Load (Pn→Qn)  
H
H
H
Count (Increment)  
No Change (Hold)  
No Change (Hold)  
X
H = HIGH Voltage Level  
L = LOW Voltage Level  
X = Immaterial  
Note 1: For 74F163A only  
Block Diagram  
3
www.fairchildsemi.com  
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与74F163ASCX相关器件

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