74F163AD

更新时间： 2024-01-24 12:13:39

品牌	Logo	应用领域
恩智浦 - NXP		计数器
页数	文件大小	规格书
14页	115K
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74F163AD 数据手册

Philips Semiconductors

Product specification

4-bit binary counters

74F161A, 74F163A

A Low level at the Master Reset (MR) input sets all the four outputs

of the flip-flops (Q0 – Q3) in 74F161A to Low levels, regardless of

the levels at CP, PE, CET and CEP inputs (thus providing an

asynchronous clear function). For the 74F163A, the clear function is

synchronous. A Low level at the Synchronous Reset (SR) input sets

all four outputs of the flip-flops (Q0 – Q3) to Low levels after the next

positive-going transition on the clock (CP) input (provided that the

setup and hold time requirements for SR are met). This action

occurs regardless of the levels at PE, CET, and CEP inputs. The

synchronous reset feature enables the designer to modify the

maximum count with only one external NAND gate (see Figure 1).

The carry look-ahead simplifies serial cascading of the counters.

Both Count Enable (CEP and CET) inputs must be High to count.

The CET input is fed forward to enable the TC output. The TC

output thus enabled will produce a High output pulse of a duration

approximately equal to the High level output of Q0. This pulse can

be used to enable the next cascaded stage (see Figure 2). The TC

output is subjected to decoding spikes due to internal race

FEATURES

• Synchronous counting and loading

• Two count enable inputs for n-bit cascading

• Positive edge-triggered clock

• Asynchronous Master Reset (74F161A)

• Synchronous Reset (74F163A)

• High speed synchronous expansion

• Typical count rate of 130MHz

• Industrial range (–40°C to +85°C) available

DESCRIPTION

4-bit binary counters feature an internal carry look-ahead and can be

used for high-speed counting. Synchronous operation is provided by

having all flip-flops clocked simultaneously on the positive-going

edge of the clock. The clock input is buffered.

conditions. Therefore, it is not recommended for use as clock or

asynchronous reset for flip-flops, registers, or counters.

The outputs of the counters may be preset to High or Low level. A

Low level at the Parallel Enable (PE) input disables the counting

action and causes the data at the D0–D3 inputs to be loaded into

the counter on the positive-going edge of the clock (provided that

the setup and hold requirements for PE are met). Preset takes place

regardless of the levels at Count Enable (CEP, CET) inputs.

TYPICAL

TYPICAL SUPPLY CURRENT

(TOTAL)

TYPE

MAX

74F161A

74F163A

130MHz

46mA

ORDERING INFORMATION

ORDER CODE

DRAWING

NUMBER

DESCRIPTION

COMMERCIAL RANGE

= 5V ±10%, T = 0°C to +70°C

INDUSTRIAL RANGE

= 5V ±10%, T

= –40°C to +85°C

amb

16-pin plastic DIP

16-pin plastic SO

N74F161AN, N74F163AN

N74F161AD, N74F163AD

I74F161AN, I74F163AN

SOT38-4

I74F161AD, I74F163AD

SOT109-1

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS

D0 – D3

CEP

CET

DESCRIPTION

74F (U.L.) HIGH/LOW

1.0/1.0

LOAD VALUE HIGH/LOW

20µA/0.6mA

Data inputs

Count Enable Parallel input

Count Enable Trickle input

Clock input (active rising edge)

Parallel Enable input (active Low)

1.0/1.0

20µA/0.6mA

1.0/2.0

20µA/1.2mA

1.0/1.0

20µA/0.6mA

1.0/2.0

20µA/1.2mA

Asynchronous Master Reset input

(active Low) for 74F161A

1.0/1.0

20µA/0.6mA

Synchronous Reset input

(active Low) for 74F163A

1.0/1.0

20µA/0.6mA

Terminal count output

Flip-flop outputs

50/33

1.0mA/20mA

Q0 – Q3

NOTE:

One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.

1996 Jan 29

853–0347 16300

123 4 5 6 7...14

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与74F163AD相关器件

型号	品牌	获取价格	描述	数据表
74F163ADC	FAIRCHILD	获取价格	Binary Counter, F/FAST Series, Synchronous, Positive Edge Triggered, 4-Bit, Up Direction,
74F163ADCQM	FAIRCHILD	获取价格	Binary Counter, Synchronous, Up Direction, TTL, CDIP16,
74F163ADCQR	TI	获取价格	F/FAST SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP16, CERAMIC, DIP-1
74F163ADCQR	FAIRCHILD	获取价格	Binary Counter, F/FAST Series, Synchronous, Positive Edge Triggered, 4-Bit, Up Direction,
74F163ADCX	TI	获取价格	F/FAST SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP16, CERAMIC, DIP-1
74F163ADMQB	TI	获取价格	F/FAST SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP16, CERAMIC, DIP-1
74F163ADMQR	TI	获取价格	F/FAST SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP16, CERAMIC, DIP-1
74F163AD-T	NXP	获取价格	暂无描述
74F163AD-T	YAGEO	获取价格	Binary Counter, F/FAST Series, Synchronous, Positive Edge Triggered, 4-Bit, Up Direction,
74F163AFCQR	TI	获取价格	F/FAST SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDFP16, CERAMIC, FP-16

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