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74F161ADCX PDF预览

74F161ADCX

更新时间： 2024-02-25 13:52:32
品牌 Logo 应用领域
德州仪器 - TI 逻辑集成电路触发器
页数 文件大小 规格书
10页 179K
描述
IC F/FAST SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP16, CERAMIC, DIP-16, Counter

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74F161ADCX 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：DIP,针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.64计数方向：UP
系列：F/FASTJESD-30 代码：R-CDIP-T16
长度：19.43 mm负载/预设输入：YES
逻辑集成电路类型：BINARY COUNTER工作模式：SYNCHRONOUS
位数：4功能数量：1
端子数量：16最高工作温度：70 °C
最低工作温度：封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：DIP封装形状：RECTANGULAR
封装形式：IN-LINE传播延迟（tpd）：11 ns
认证状态：Not Qualified座面最大高度：5.08 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：TTL温度等级：COMMERCIAL
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL触发器类型：POSITIVE EDGE
宽度：7.62 mm最小 fmax：90 MHz
Base Number Matches：1

74F161ADCX 数据手册

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Functional Description  
The ’F161A and ’F163A count in modulo-16 binary se-  
quence. From state 15 (HHHH) they increment to state 0  
(LLLL). The clock inputs of all flip-flops are driven in parallel  
through a clock buffer. Thus all changes of the Q outputs  
(except due to Master Reset of the ’F161A) occur as a re-  
sult of, and synchronous with, the LOW-to-HIGH transition  
of the CP input signal. The circuits have four fundamental  
modes of operation, in order of precedence: asynchronous  
reset (’F161A), synchronous reset (’F163A), parallel load,  
count-up and hold. Five control inputsÐMaster Reset (MR,  
’F161A), Synchronous Reset (SR, ’F163A), Parallel Enable  
(PE), Count Enable Parallel (CEP) and Count Enable Trickle  
(CET)Ðdetermine the mode of operation, as shown in the  
Mode Select Table. A LOW signal on MR overrides all other  
inputs and asynchronously forces all outputs LOW. A LOW  
signal on SR overrides counting and parallel loading and  
allows all outputs to go LOW on the next rising edge of CP.  
A LOW signal on PE overrides counting and allows informa-  
flip-flops on the next rising edge of CP. With PE and MR  
(’F161A) or SR (’F163A) HIGH, CEP and CET permit count-  
ing when both are HIGH. Conversely, a LOW signal on ei-  
ther CEP or CET inhibits counting.  
The ’F161A and ’F163A use D-type edge triggered flip-flops  
and changing the SR, PE, CEP and CET inputs when the CP  
is in either state does not cause errors, provided that the  
recommended setup and hold times, with respect to the ris-  
ing edge of CP, are observed.  
The Terminal Count (TC) output is HIGH when CET is HIGH  
and the counter is in state 15. To implement synchronous  
multi-stage counters, the TC outputs can be used with the  
CEP and CET inputs in two different ways. Please refer to  
the ’F568 data sheet. The TC output is subject to decoding  
spikes due to internal race conditions and is therefore not  
recommended for use as a clock or asynchronous reset for  
flip-flops, counters or registers.  
e
Logic Equations: Count Enable  
CEP CET PE  
#
#
CET  
tion on the Parallel Data (P ) inputs to be loaded into the  
n
e
TC  
Q
Q
Q
Q
#
#
#
#
3
0
1
2
State Diagram  
Mode Select Table  
Action on the Rising  
*SR  
PE  
CET  
CEP  
Clock Edge (L)  
L
H
H
H
H
X
L
X
X
H
L
X
X
H
X
L
Reset (Clear)  
Load (PnxQ )  
n
H
H
H
Count (Increment)  
No Change (Hold)  
No Change (Hold)  
X
*For ’F163A only  
e
e
e
H
HIGH Voltage Level  
L
LOW Voltage Level  
Immaterial  
X
TL/F/9486–5  
3
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