74F161ADCQM

更新时间： 2024-02-23 18:13:57

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		计数器
页数	文件大小	规格书
8页	96K
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数据手册

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74F161ADCQM 数据手册

Functional Description

The 74F161A and 74F163A count in modulo-16 binary

sequence. From state 15 (HHHH) they increment to state 0

(LLLL). The clock inputs of all flip-flops are driven in paral-

lel through a clock buffer. Thus all changes of the Q outputs

(except due to Master Reset of the 74F161A) occur as a

result of, and synchronous with, the LOW-to-HIGH transi-

tion of the CP input signal. The circuits have four funda-

mental modes of operation, in order of precedence:

asynchronous reset (74F161A), synchronous reset

(74F163A), parallel load, count-up and hold. Five control

inputs—Master Reset (MR, 74F161A), Synchronous Reset

(SR, 74F163A), Parallel Enable (PE), Count Enable Paral-

lel (CEP) and Count Enable Trickle (CET)—determine the

mode of operation, as shown in the Mode Select Table. A

LOW signal on MR overrides all other inputs and asynchro-

nously forces all outputs LOW. A LOW signal on SR over-

rides counting and parallel loading and allows all outputs to

go LOW on the next rising edge of CP. A LOW signal on PE

overrides counting and allows information on the Parallel

Data (P_n) inputs to be loaded into the flip-flops on the next

rising edge of CP. With PE and MR ('F161A) or SR

(74F163A) HIGH, CEP and CET permit counting when

both are HIGH. Conversely, a LOW signal on either CEP or

CET inhibits counting.

The 74F161A and 74F163A use D-type edge triggered flip-

flops and changing the SR, PE, CEP and CET inputs when

the CP is in either state does not cause errors, provided

that the recommended setup and hold times, with respect

to the rising edge of CP, are observed.

The Terminal Count (TC) output is HIGH when CET is

HIGH and the counter is in state 15. To implement synchro-

nous multi-stage counters, the TC outputs can be used

with the CEP and CET inputs in two different ways. Please

refer to the 74F568 data sheet. The TC output is subject to

decoding spikes due to internal race conditions and is

therefore not recommended for use as a clock or asynchro-

nous reset for flip-flops, counters or registers.

Logic Equations: Count Enable = CEP • CET • PE

TC = Q₀• Q₁• Q₂• Q₃• CET

Mode Select Table

State Diagram

Action on the Rising

Clock Edge (

Reset (Clear)

(Note 1)

PE CET

)

Load (P_n→Q_n)

Count (Increment)

No Change (Hold)

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

Note 1: For 74F163A only

Block Diagram

www.fairchildsemi.com

1 234 5 6 7 8

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