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74ACT11544NT PDF预览

74ACT11544NT

更新时间: 2024-01-15 21:15:55
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
8页 107K
描述
Octal Registered Transceivers With 3-State Outputs 28-PDIP -40 to 85

74ACT11544NT 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:DIP
包装说明:DIP, DIP28,.3针数:28
Reach Compliance Code:not_compliant风险等级:5.86
其他特性:INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; MASTER CONTROL FOR LATCH控制类型:INDEPENDENT CONTROL
计数方向:BIDIRECTIONAL系列:ACT
JESD-30 代码:R-PDIP-T28长度:35.69 mm
逻辑集成电路类型:REGISTERED BUS TRANSCEIVER位数:8
功能数量:1端口数量:2
端子数量:28最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP28,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
传播延迟(tpd):11 ns认证状态:Not Qualified
座面最大高度:5.08 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
翻译:N/A宽度:7.62 mm
Base Number Matches:1

74ACT11544NT 数据手册

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ꢀ ꢁ ꢂꢃ ꢄꢅꢅꢆ ꢁꢁ  
ꢇ ꢃꢄꢂꢈꢉꢊ ꢋꢌ ꢍꢎ ꢄꢋ ꢊꢋꢏꢉ ꢄ ꢊꢂꢐ ꢎꢃ ꢋ ꢍꢑ ꢋꢊ  
ꢒ ꢍꢄ ꢓꢉ ꢔ ꢕꢎꢄꢂꢄ ꢋꢉ ꢇꢖ ꢄꢗ ꢖꢄ ꢎ  
SCAS133 − D3609, JULY 1990 − REVISED APRIL 1993  
DW PACKAGE  
(TOP VIEW)  
Inputs Are TTL-Voltage Compatible  
3-State Inverted Outputs  
Back-to-Back Registers for Storage  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
CEBA  
A1  
GBA  
LEBA  
B1  
Flow-Through Architecture Optimizes  
2
PCB Layout  
3
A2  
A3  
A4  
GND  
GND  
GND  
GND  
A5  
Center-Pin V  
and GND Configurations  
Minimize High-Speed Switching Noise  
CC  
4
B2  
5
B3  
EPICt (Enhanced-Performance Implanted  
CMOS) 1-mm Process  
6
B4  
7
V
V
CC  
CC  
8
500-mA Typical Latch-Up Immunity  
at 125°C  
9
B5  
10  
11  
12  
13  
14  
B6  
B7  
B8  
LEAB  
GAB  
description  
A6  
A7  
A8  
This 8-bit registered transceiver contains two sets  
of D-type latches for temporary storage of data  
flowing in either direction. Separate latch enable  
(LEAB or LEBA) and output enable (GAB or GBA)  
inputs are provided for each register to permit  
independent control in either direction of data flow.  
The 74ACT11544 inverts data in both directions.  
CEAB  
The A-to-B enable (CEAB) input must be low in order to enter data from A or to output data to B. Having CEAB  
low and LEAB low makes the A-to-B latches transparent; a subsequent low-to-high transition of LEAB puts the  
A latches in the storage mode. With CEAB and GAB both low, the 3-state B outputs are active and reflect the  
data present at the output of the A latches. Data flow from B-to-A is similar, but requires the use of CEBA, LEBA,  
and GBA inputs.  
The 74ACT11544 is characterized for operation from 40°C to 85°C.  
FUNCTION TABLE  
LATCH  
INPUTS  
LEAB  
OUTPUT BUFFERS  
B1 THRU B8  
STATUS  
CEAB  
GAB  
A TO B  
H
X
X
L
X
H
X
Storing  
Storing  
Z
H
L
L
Z
L
Transparent  
Storing  
Current A Data  
}
L
H
Previous A Data  
A-to-B data flow is shown: B-to-A flow control is the same except uses  
CEBA, LEBA, and GBA.  
Data present before low-to-high transition of LEAB.  
EPIC is a trademark of Texas Instruments Incorporated.  
ꢄꢤ  
Copyright 1993, Texas Instruments Incorporated  
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ  
2−1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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