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74AC169SCT

更新时间： 2024-02-07 08:48:54

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		计数器
页数	文件大小	规格书
8页	106K
描述
Binary Counter, AC Series, Synchronous, Positive Edge Triggered, 4-Bit, Bidirectional, CMOS, PDSO16, SOIC-16

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技术参数
数据手册

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74AC169SCT 技术参数

生命周期：	Transferred	包装说明：	SOP,
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.68	Is Samacsys：	N
其他特性：	TCO OUTPUT	计数方向：	BIDIRECTIONAL
系列：	AC	JESD-30 代码：	R-PDSO-G16
长度：	10.11 mm	负载电容（CL）：	50 pF
负载/预设输入：	YES	逻辑集成电路类型：	BINARY COUNTER
工作模式：	SYNCHRONOUS	位数：	4
功能数量：	1	端子数量：	16
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
传播延迟（tpd）：	12 ns	认证状态：	Not Qualified
座面最大高度：	2.108 mm	最大供电电压 (Vsup)：	6 V
最小供电电压 (Vsup)：	2 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
触发器类型：	POSITIVE EDGE	宽度：	5.3 mm
最小 fmax：	90 MHz	Base Number Matches：	1

74AC169SCT 数据手册

Functional Description

Mode Select Table

The AC169 uses edge-triggered J-K-type flip-flops and

have no constraints on changing the control or data input

signals in either state of the Clock. The only requirement is

that the various inputs attain the desired state at least a

setup time before the rising edge of the clock and remain

valid for the recommended hold time thereafter. The paral-

lel load operation takes precedence over the other opera-

tions, as indicated in the Mode Select Table. When PE is

LOW, the data on the P₀–P₃inputs enters the flip-flops on

Action on Rising

Clock Edge

CEP CET

U/D

Load (P_nto Q_n)

Count Up (Increment)

Count Down (Decrement)

No Change (Hold)

the next rising edge of the Clock. In order for counting to

occur, both CEP and CET must be LOW and PE must be

HIGH; the U/D input then determines the direction of count-

ing. The Terminal Count (TC) output is normally HIGH and

goes LOW, provided that CET is LOW, when a counter

reaches zero in the Count Down mode or reaches 15 in the

Count Up mode. The TC output state is not a function of

the Count Enable Parallel (CEP) input level. If an illegal

state occurs, the AC169 will return to the legitimate

sequence within two counts. Since the TC signal is derived

by decoding the flip-flop states, there exists the possibility

of decoding spikes on TC. For this reason the use of TC as

a clock signal is not recommended (see logic equations

below).

No Change (Hold)

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

State Diagram

1. Count Enable = CEP •CET • PE

2. Up: TC = Q₀•Q₁•Q ₂Q₃•(Up)•CET

3. Down: TC = Q₀• Q₁•Q₂•Q₃•(Down)•CET

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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与74AC169SCT相关器件

型号	品牌	描述	获取价格	数据表
74AC169SCTR	FAIRCHILD	Binary Counter, AC Series, Synchronous, Positive Edge Triggered, 4-Bit, Bidirectional, CMO	获取价格
74AC169SCX	FAIRCHILD	Synchronous Up/Down Counter	获取价格
74AC169SCX_NL	FAIRCHILD	Binary Counter, AC Series, Synchronous, Positive Edge Triggered, 4-Bit, Bidirectional, CMO	获取价格
74AC169SCXR	FAIRCHILD	Binary Counter, AC Series, Synchronous, Positive Edge Triggered, 4-Bit, Bidirectional, CMO	获取价格
74AC169SJ	FAIRCHILD	Synchronous Up/Down Counter	获取价格
74AC169SJX	FAIRCHILD	Synchronous Up/Down Counter	获取价格

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