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74AC11074PWRE4 PDF预览

74AC11074PWRE4

更新时间: 2024-01-20 11:22:26
品牌 Logo 应用领域
德州仪器 - TI 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
15页 668K
描述
Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset 14-TSSOP -40 to 85

74AC11074PWRE4 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:GREEN, PLASTIC, TSSOP-14针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.57Is Samacsys:N
系列:ACJESD-30 代码:R-PDSO-G14
JESD-609代码:e4长度:5 mm
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:100000000 Hz最大I(ol):0.024 A
湿度敏感等级:1位数:1
功能数量:2端子数量:14
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:3.3/5 V传播延迟(tpd):11.3 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:4.4 mm
最小 fmax:125 MHzBase Number Matches:1

74AC11074PWRE4 数据手册

 浏览型号74AC11074PWRE4的Datasheet PDF文件第2页浏览型号74AC11074PWRE4的Datasheet PDF文件第3页浏览型号74AC11074PWRE4的Datasheet PDF文件第4页浏览型号74AC11074PWRE4的Datasheet PDF文件第5页浏览型号74AC11074PWRE4的Datasheet PDF文件第6页浏览型号74AC11074PWRE4的Datasheet PDF文件第7页 
ꢀꢁ ꢂꢃ ꢄꢄꢅ ꢀꢁ  
ꢆꢇꢂ ꢈ ꢉꢊ ꢋꢌ ꢍ ꢌꢎꢏ ꢐꢏꢆꢑ ꢏꢐꢍ ꢒꢌ ꢑ ꢑꢏ ꢒꢏꢆ ꢆꢐꢍ ꢓꢉ ꢏ ꢔ ꢈꢌ ꢉ ꢐꢔ ꢈꢊ ꢉ  
ꢕ ꢌꢍ ꢖ ꢃꢈ ꢏꢂꢒ ꢂꢗꢆ ꢉ ꢒꢏ ꢋ ꢏꢍ  
SCAS499A − DECEMBER 1986 − REVISED APRIL 1996  
D, N, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
D
Center-Pin V  
Minimize High-Speed Switching Noise  
and GND Configurations  
CC  
EPIC(Enhanced-Performance Implanted  
CMOS) 1-µm Process  
500-mA Typical Latch-Up Immunity at  
1PRE  
1Q  
1CLK  
1D  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1Q  
1CLR  
125°C  
GND  
2Q  
2Q  
V
2CLR  
2D  
CC  
Package Options Include Plastic  
Small-Outline (D) and Thin Shrink  
Small-Outline (PW) Packages, and  
Standard Plastic 300-mil DIPs (N)  
2PRE  
2CLK  
8
description  
This device contains two independent positive-edge-triggered D-type flip-flops. A low level at the preset (PRE)  
or clear (CLR) input sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR  
are inactive (high), data at the data (D) input that meets the setup-time requirements are transferred to the  
outputs on the low-to-high transition of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is  
not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input may  
be changed without affecting the levels at the outputs.  
The 74AC11074 is characterized for operation from −40°C to 85°C.  
FUNCTION TABLE  
INPUTS  
OUTPUT  
PRE  
L
CLR  
CLK  
X
D
X
X
X
H
L
Q
H
L
Q
H
L
L
H
X
H
H
L
L
X
H
H
H
H
H
°
H
L
L
H
°
H
H
L
X
Q
Q
0
0
This configuration is nonstable; that is, it does not  
persist when PRE or CLR returns to its inactive  
(high) level.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
ꢍꢣ  
Copyright 1996, Texas Instruments Incorporated  
ꢟ ꢣ ꢠ ꢟꢘ ꢙꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢨ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

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