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73S8014RN

更新时间： 2024-01-29 00:56:45

品牌	Logo	应用领域
TERIDIAN		/
页数	文件大小	规格书
28页	403K
描述
Smart Card Interface

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技术参数
数据手册

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73S8014RN 技术参数

生命周期：	Transferred	包装说明：	ROHS COMPLIANT, SOP-20
Reach Compliance Code：	unknown	风险等级：	5.59
模拟集成电路 - 其他类型：	ANALOG CIRCUIT	JESD-30 代码：	R-PDSO-G20
长度：	12.76 mm	功能数量：	1
端子数量：	20	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	认证状态：	Not Qualified
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	2.7 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	宽度：	7.51 mm
Base Number Matches：	1

73S8014RN 数据手册

73S8014RN Data Sheet

DS_8014RN_014

Table 1 provides the 73S8014RN pin names, pin numbers, type, equivalent circuits and descriptions.

Table 1: 73S8014RN 20-Pin SOP Pin Definitions

Number

Equivalent

Circuit

Pin Name

Card Interface

I/O

Type

Description

Card I/O: Data signal to/from card. Includes an 11K pull-up

resistor to V_CC.

Figure 14

RST

Figure 13 Card reset: provides reset (RST) signal to card.

Card clock: provides clock signal (CLK) to card. The rate of this

clock is determined by the external crystal frequency or

frequency of the external clock signal applied on XTALIN and

CLKDIV selections.

CLK

Figure 12

Card Presence switch: active high indicates card is present.

Figure 16

PRES

Includes a high-impedance pull-down current source.

Card power supply – logically controlled by sequencer, output of

Figure 11 LDO regulator. Requires an external filter capacitor to the card

GND.

VCC

GND

PSO

GND

–

Card ground.

Host Processor Interface

Command VCC (negative assertion): Logic low on this pin

CMDVCC

Figure 16 causes the LDO regulator to ramp the V_CCsupply to the card

and initiates a card activation sequence, if a card is present.

5 volt / 3 volt card selection: Logic high selects 5 volts for V_CC

and card interface, logic low selects 3 volt operation. When the

part is to be used with a single card voltage, this pin should be

Figure 16 tied to either GND or V_DD. However, it includes a high

impedance pull-up resistor to default this pin high (selection of

5V card) when not connected. This pin shall not be changed

when CMDVCC is low.

5V/#V

Sets the divide ratio from the XTAL oscillator (or external clock

input) to the card clock. These pins include a pull-up resistor for

CLKDIV1 and CLKLDIV2 to provide a default rate of divide by

two.

CLKDIV1

CLKDIV2

Figure 16

CLKDIV1

CLKDIV2

CLOCK RATE

XTALIN/6

XTALIN/4

XTALIN/2

XTALIN

Interrupt signal to the processor. Active Low - Multi-function

OFF

Figure 10 indicating fault conditions and card presence. Open drain output

configuration – It includes an internal 20kΩ pull-up to V_DD.

RSTIN

I/OUC

Figure 16 Reset Input: This signal is the reset command to the card.

System controller data I/O to/from the card. Includes an 11K

Figure 15

pull-up resistor to V_DD.

Rev. 1.0

1...3 4 567 8 9...28

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与73S8014RN相关器件

型号	品牌	描述	获取价格	数据表
73S8014RN-IL/F	TERIDIAN	Smart Card Interface	获取价格
73S8014RN-IL/F2	MAXIM	Analog Circuit, 1 Func, PDSO20, SOP-20	获取价格
73S8014RN-ILR/F	TERIDIAN	Smart Card Interface	获取价格
73S8014RN-ILR/F2	MAXIM	Analog Circuit, 1 Func, PDSO20, SOP-20	获取价格
73S8014RN-ILR/F3	MAXIM	Analog Circuit, 1 Func, PDSO20, SOP-20	获取价格
73S8014RT	TERIDIAN	Smart Card Interface	获取价格

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