Datasheet > 73S8010R-IMR/F2

73S8010R-IMR/F2

更新时间： 2024-01-24 13:44:06

品牌	Logo	应用领域
美信 - MAXIM		PC
页数	文件大小	规格书
25页	330K
描述
Analog Circuit, 1 Func, 5 X 5 MM, 0.80 MM HEIGHT, LEAD FREE, QFN-32

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73S8010R-IMR/F2 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	HVQCCN,	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.65
Samacsys Confidence：		Samacsys Status：	Released
Schematic Symbol：	https://componentsearchengine.com/symbol.php?partID=599366	PCB Footprint：	https://componentsearchengine.com/footprint.php?partID=599366
Samacsys PartID：	599366	Samacsys Image：	https://componentsearchengine.com/Images/9/73S8010R-IMR/F2.jpg
Samacsys Thumbnail Image：	https://componentsearchengine.com/Thumbnails/1/73S8010R-IMR/F2.jpg	Samacsys Pin Count：	33
Samacsys Part Category：	Integrated Circuit	Samacsys Package Category：	Other
Samacsys Footprint Name：	QFN50P500X500X90-33N	Samacsys Released Date：	2017-01-11 21:24:41
Is Samacsys：	N	模拟集成电路 - 其他类型：	ANALOG CIRCUIT
JESD-30 代码：	S-XQCC-N32	长度：	5 mm
功能数量：	1	端子数量：	32
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	UNSPECIFIED	封装代码：	HVQCCN
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	NOT SPECIFIED	座面最大高度：	0.9 mm
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	2.7 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	5 mm	Base Number Matches：	1

73S8010R-IMR/F2 数据手册

73S8010R Data Sheet

DS_8010R_022

Figures

Figure 1: 73S8010R Block Diagram.........................................................................................................2

Figure 2: 73S8010R 32-Pin QFN Pinout ..................................................................................................5

Figure 3: 73S8010R 28-Pin SO Pinout.....................................................................................................5

Figure 4: Typical 73S8010R Application Schematic ...............................................................................13

Figure 5: I²C Bus Write Protocol ............................................................................................................15

Figure 6: I²C Bus Read Protocol ............................................................................................................16

Figure 7: I²C Bus Timing Diagram..........................................................................................................16

Figure 8: Activation Sequence...............................................................................................................19

Figure 9: Deactivation Sequence...........................................................................................................20

Figure 10: Interrupt operation due to Fault and Status Conditions ..........................................................20

Figure 11: Warm Reset Operation .........................................................................................................21

Figure 12: I/O Timing Diagram...............................................................................................................21

Figure 13: 32-pin QFN Package Dimensions .........................................................................................22

Figure 14: 28-Pin SO Package Dimensions ...........................................................................................23

Tables

Table 1: 73S8010R Pin Definitions ..........................................................................................................6

Table 2: Absolute Maximum Device Ratings ............................................................................................8

Table 3: Recommended Operating Conditions.........................................................................................8

Table 4: DC Smart Card Interface Requirements .....................................................................................9

Table 5: Digital Signals Characteristics ..................................................................................................11

Table 6: DC Characteristics ...................................................................................................................11

Table 7: I²C Characteristics ...................................................................................................................12

Table 8: Voltage / Temperature Fault Detection Circuits.........................................................................12

Table 9: Device Address Selection ........................................................................................................14

Table 10: Control Register Description...................................................................................................14

Table 11: Card Clock Rate Selection .....................................................................................................14

Table 12: Status Register Description....................................................................................................15

Table 13: I2C Bus Timing Parameters ...................................................................................................16

Table 14: Choice of VCC Pin Capacitor .................................................................................................18

Table 15: Card Clock Divisor Options ....................................................................................................18

Table 16: Order Numbers and Packaging Marks....................................................................................24

Rev. 1.6

1 2 345 6 7...25

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